@samitouri / QOSamiQemu / commits / 78f51b0ea5

disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32

These entire base opcodes are RV64. Reject them all at once rather than one at a time. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260812223142.349142-38-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Richard Henderson committed Aug 12, 2026 at 15:31 UTC 78f51b0ea5205bda472652b326caf439d92a2c3b

1 file changed +8

disas/riscv.c

@@ -3311,6 +3311,10 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)

3311 }

3312 break;

3313 case 6:

3314 + /* OP-IMM-32 */

3315 + if (isa == rv32) {

3316 + break;

3317 + }

3318 switch ((inst >> 12) & 0b111) {

3319 case 0: op = rv_op_addiw; break;

3320 case 1:

@@ -3557,6 +3561,10 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)

3561 break;

3562 case 13: op = rv_op_lui; break;

3563 case 14:

3564 + /* OP-32 */

3565 + if (isa == rv32) {

3566 + break;

3567 + }

3568 switch (((inst >> 22) & 0b1111111000) |

3569 ((inst >> 12) & 0b0000000111)) {

3570 case 0: op = rv_op_addw; break;