@samitouri / QOSamiQemu / commits / 7a8454ef29

disas/riscv: Fix 6-bit immediate extraction

rv_codec_r2_imm6 is used for XThead instructions whose 6-bit immediate field is encoded in bits 25:20. The old expression left-shifted by 38 and then right-shifted by 60, so it kept only bits 25:22. Use extract32() to decode bits 25:20 directly. This fixes the immediate printed for th.srri and th.tst. Fixes: 318df7238b9f ("disas/riscv: Add support for XThead* instructions") Suggested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260703-b4-disas-xthead-fix-riscv-next-v4-2-84c566330bc7@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

TANG Tiancheng committed Jul 3, 2026 at 13:03 UTC 7a8454ef293085a45686929577b7d5a5daded242
1 file changed +1 -1
disas/riscv.c
+1 -1
@@ -4546,7 +4546,7 @@ static uint32_t operand_zcmp_rlist(rv_inst inst)
4546
4547 static uint32_t operand_imm6(rv_inst inst)
4548 {
4549 - return (inst << 38) >> 60;
4549 + return extract32(inst, 20, 6);
4550 }
4551
4552 static uint32_t operand_imm2(rv_inst inst)