target/arm: Add FGWTE3 FGT bit definitions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260806172709.333300-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 6, 2026 at 10:27 UTC
7a8d5411fd5fb8c76affe4ef82f96d70d5a38246
1 file changed
+31
target/arm/cpregs.h
+31
@@ -728,6 +728,9 @@ FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */
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#define DO_BIT(REG, BITNAME) \
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FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT
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+#define DO_EL3_BIT(REG, BITNAME) \
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+ FGT_##BITNAME = FGT_##REG | R_##REG##_EL3_##BITNAME##_SHIFT
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+
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/* Some bits have reversed sense, so 0 means trap and 1 means not */
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#define DO_REV_BIT(REG, BITNAME) \
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FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
@@ -787,6 +790,7 @@ typedef enum FGTBit {
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FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
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FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
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FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
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+ FGT_FGWTE3 = FGT_W | (FGTREG_FGWTE3 << R_FGT_IDX_SHIFT),
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/* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */
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DO_BIT(HFGRTR, AFSR0_EL1),
@@ -919,10 +923,37 @@ typedef enum FGTBit {
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DO_REV_BIT(HFGITR, NGCSPUSHM_EL1),
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DO_REV_BIT(HFGITR, NGCSEPP),
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DO_BIT(HFGITR, ATS1E1A),
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+
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+ /* Trap bits in FGWTE3_EL3, starting from bit 0 */
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+ DO_EL3_BIT(FGWTE3, ACTLR_EL3),
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+ DO_EL3_BIT(FGWTE3, AFSR0_EL3),
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+ DO_EL3_BIT(FGWTE3, AFSR1_EL3),
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+ DO_EL3_BIT(FGWTE3, AMAIR_EL3),
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+ DO_EL3_BIT(FGWTE3, AMAIR2_EL3),
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+ DO_EL3_BIT(FGWTE3, GCSCR_EL3),
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+ DO_EL3_BIT(FGWTE3, GCSPR_EL3),
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+ DO_EL3_BIT(FGWTE3, GPCCR_EL3),
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+ DO_EL3_BIT(FGWTE3, GPTBR_EL3),
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+ DO_EL3_BIT(FGWTE3, MAIR_EL3),
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+ DO_EL3_BIT(FGWTE3, MAIR2_EL3),
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+ DO_EL3_BIT(FGWTE3, MDCR_EL3),
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+ DO_EL3_BIT(FGWTE3, MECID_RL_A_EL3),
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+ DO_EL3_BIT(FGWTE3, MPAM3_EL3),
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+ DO_EL3_BIT(FGWTE3, PIR_EL3),
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+ DO_EL3_BIT(FGWTE3, SCTLR_EL3),
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+ DO_EL3_BIT(FGWTE3, SCTLR2_EL3),
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+ DO_EL3_BIT(FGWTE3, SPMROOTCR_EL3),
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+ DO_EL3_BIT(FGWTE3, TCR_EL3),
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+ DO_EL3_BIT(FGWTE3, TPIDR_EL3),
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+ DO_EL3_BIT(FGWTE3, TTBR0_EL3),
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+ DO_EL3_BIT(FGWTE3, VBAR_EL3),
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+ DO_EL3_BIT(FGWTE3, GPCBW_EL3),
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} FGTBit;
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#undef DO_BIT
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+#undef DO_EL3_BIT
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#undef DO_REV_BIT
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+#undef DO_TLBINXS_BIT
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typedef struct ARMCPRegInfo ARMCPRegInfo;
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