target/riscv/kvm: Synchronize privilege mode
The KVM core register synchronization currently omits the vCPU privilege mode. As a result, env.priv can be stale when the migration stream is saved and the destination can restore the vCPU in the wrong mode. Read and write the KVM core mode register together with the other core registers. The generic RISC-V CPU VMState already carries env.priv, so no migration format change is required. Signed-off-by: Xie Bo <xb@ultrarisc.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260808125157.1220511-2-xb@ultrarisc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Xie Bo committed
Aug 8, 2026 at 20:51 UTC
7df9aa5f6d600584c556776505253e849b3902ee
1 file changed
+12
target/riscv/kvm/kvm-cpu.c
+12
@@ -603,6 +603,12 @@ static int kvm_riscv_get_regs_core(CPUState *cs)
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}
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env->pc = reg;
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+ ret = kvm_get_one_reg(cs, RISCV_CORE_REG(mode), ®);
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+ if (ret) {
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+ return ret;
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+ }
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+ env->priv = reg;
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+
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for (i = 1; i < 32; i++) {
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uint64_t id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i);
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ret = kvm_get_one_reg(cs, id, ®);
@@ -628,6 +634,12 @@ static int kvm_riscv_put_regs_core(CPUState *cs)
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return ret;
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}
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+ reg = env->priv;
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+ ret = kvm_set_one_reg(cs, RISCV_CORE_REG(mode), ®);
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+ if (ret) {
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+ return ret;
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+ }
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+
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for (i = 1; i < 32; i++) {
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uint64_t id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i);
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reg = env->gpr[i];