cpu: Rename CPUState @singlestep_enabled -> @singlestep_flags
CPUState::singlestep_enabled contains multiple flags since commit 60897d369f1 ("Debugger single step without interrupts"). Use an unsigned type and rename the field to avoid mistakes. Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260705215729.62196-32-philmd@oss.qualcomm.com>
Philippe Mathieu-Daudé committed
Jun 26, 2026 at 14:25 UTC
7e28b7c8970ce2740a665156927f3c3cda82fc2e
7 files changed
+21
-21
accel/kvm/kvm-all.c
+1
-1
@@ -3815,7 +3815,7 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap)
3815
if (cpu_single_stepping(cpu)) {
3816
data.dbg.control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_SINGLESTEP;
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- if (cpu->singlestep_enabled & SSTEP_NOIRQ) {
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+ if (cpu->singlestep_flags & SSTEP_NOIRQ) {
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data.dbg.control |= KVM_GUESTDBG_BLOCKIRQ;
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}
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}
accel/tcg/cpu-exec.c
+1
-1
@@ -828,7 +828,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
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return true;
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}
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- if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
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+ if (unlikely(cpu->singlestep_flags & SSTEP_NOIRQ)) {
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/* Mask out external interrupts for this step. */
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interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
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}
accel/tcg/tcg-accel-ops-rr.c
+1
-1
@@ -274,7 +274,7 @@ static void *rr_cpu_thread_fn(void *arg)
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current_cpu = cpu;
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qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
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- (cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);
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+ (cpu->singlestep_flags & SSTEP_NOTIMER) == 0);
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if (cpu_can_run(cpu)) {
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int r;
cpu-target.c
+4
-4
@@ -28,12 +28,12 @@
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/* enable or disable single step mode. EXCP_DEBUG is returned by the
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CPU loop after each instruction */
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-void cpu_single_step(CPUState *cpu, int enabled)
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+void cpu_single_step(CPUState *cpu, unsigned flags)
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{
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- if (cpu->singlestep_enabled != enabled) {
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+ if (cpu->singlestep_flags != flags) {
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trace_cpu_change_singlestep_flags(cpu->cpu_index,
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- cpu->singlestep_enabled, enabled);
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- cpu->singlestep_enabled = enabled;
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+ cpu->singlestep_flags, flags);
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+ cpu->singlestep_flags = flags;
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#if !defined(CONFIG_USER_ONLY)
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const AccelOpsClass *ops = cpus_get_accel();
include/hw/core/cpu.h
+5
-5
@@ -440,7 +440,7 @@ struct qemu_work_item;
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* @stopped: Indicates the CPU has been artificially stopped.
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* @unplug: Indicates a pending CPU unplug request.
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* @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
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- * @singlestep_enabled: Flags for single-stepping.
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+ * @singlestep_flags: Flags for single-stepping.
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* @icount_extra: Instructions until next timer event.
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* @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
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* AddressSpaces this CPU has)
@@ -505,7 +505,7 @@ struct CPUState {
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int exclusive_context_count;
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uint32_t cflags_next_tb;
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uint32_t interrupt_request;
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- int singlestep_enabled;
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+ unsigned singlestep_flags;
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int64_t icount_budget;
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int64_t icount_extra;
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uint64_t random_seed;
@@ -1132,11 +1132,11 @@ void qemu_init_vcpu(CPUState *cpu);
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/**
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* cpu_single_step:
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* @cpu: CPU to the flags for.
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- * @enabled: Flags to enable.
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+ * @flags: Flags to enable.
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*
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* Enables or disables single-stepping for @cpu.
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*/
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-void cpu_single_step(CPUState *cpu, int enabled);
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+void cpu_single_step(CPUState *cpu, unsigned flags);
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/**
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* cpu_single_stepping:
@@ -1146,7 +1146,7 @@ void cpu_single_step(CPUState *cpu, int enabled);
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*/
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static inline bool cpu_single_stepping(const CPUState *cpu)
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{
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- return cpu->singlestep_enabled;
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+ return cpu->singlestep_flags;
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}
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int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
target/arm/hvf/hvf.c
+1
-1
@@ -2603,7 +2603,7 @@ int hvf_arch_vcpu_exec(CPUState *cpu)
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flush_cpu_state(cpu);
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do {
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- if (!(cpu->singlestep_enabled & SSTEP_NOIRQ) &&
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+ if (!(cpu->singlestep_flags & SSTEP_NOIRQ) &&
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hvf_inject_interrupts(cpu)) {
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return EXCP_INTERRUPT;
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}
target/ppc/translate.c
+8
-8
@@ -198,7 +198,7 @@ struct DisasContext {
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bool pmu_insn_cnt;
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bool bhrb_enable;
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ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
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- int singlestep_enabled;
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+ int singlestep_flags;
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uint32_t flags;
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uint64_t insns_flags;
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uint64_t insns_flags2;
@@ -367,7 +367,7 @@ static void gen_debug_exception(DisasContext *ctx, bool rfi_type)
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#if !defined(CONFIG_USER_ONLY)
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if (ctx->flags & POWERPC_FLAG_DE) {
369
target_ulong dbsr = 0;
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- if (ctx->singlestep_enabled & CPU_SINGLE_STEP) {
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+ if (ctx->singlestep_flags & CPU_SINGLE_STEP) {
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dbsr = DBCR0_ICMP;
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} else {
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/* Must have been branch */
@@ -3645,7 +3645,7 @@ static void pmu_count_insns(DisasContext *ctx)
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static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
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{
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- if (unlikely(ctx->singlestep_enabled)) {
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+ if (unlikely(ctx->singlestep_flags)) {
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return false;
3650
}
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return translator_use_goto_tb(&ctx->base, dest);
@@ -3653,7 +3653,7 @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
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static void gen_lookup_and_goto_ptr(DisasContext *ctx)
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{
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- if (unlikely(ctx->singlestep_enabled)) {
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+ if (unlikely(ctx->singlestep_flags)) {
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gen_debug_exception(ctx, false);
3658
} else {
3659
/*
@@ -6559,13 +6559,13 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1;
6560
ctx->bhrb_enable = (hflags >> HFLAGS_BHRB_ENABLE) & 1;
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- ctx->singlestep_enabled = 0;
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+ ctx->singlestep_flags = 0;
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if ((hflags >> HFLAGS_SE) & 1) {
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- ctx->singlestep_enabled |= CPU_SINGLE_STEP;
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+ ctx->singlestep_flags |= CPU_SINGLE_STEP;
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ctx->base.max_insns = 1;
6566
}
6567
if ((hflags >> HFLAGS_BE) & 1) {
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- ctx->singlestep_enabled |= CPU_BRANCH_STEP;
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+ ctx->singlestep_flags |= CPU_BRANCH_STEP;
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}
6570
}
6571
@@ -6641,7 +6641,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
6641
}
6642
6643
/* Honor single stepping. */
6644
- if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) {
6644
+ if (unlikely(ctx->singlestep_flags & CPU_SINGLE_STEP)) {
6645
bool rfi_type = false;
6646
6647
switch (is_jmp) {