tcg/aarch64: Use tgen_brcondi in tcg_out_qemu_ldst_i128
Allow tgen_brcondi to choose between TBNZ and TST+B.cond for implementing a particular mask. Suggested-by: yujun <yujun@kylinos.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson committed
Jul 24, 2026 at 19:51 UTC
7f9ce196f71ffded121f26ae6df5e6036eda5e1f
1 file changed
+10
-15
tcg/aarch64/tcg-target.c.inc
+10
-15
@@ -1916,23 +1916,18 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
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use_pair = h.aa.atom < MO_128 || have_lse2;
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if (!use_pair) {
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- tcg_insn_unit *branch = NULL;
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+ TCGLabel *label = NULL;
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TCGReg ll, lh, sl, sh;
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-
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/*
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- * If we have already checked for 16-byte alignment, that's all
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- * we need. Otherwise we have determined that misaligned atomicity
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- * may be handled with two 8-byte loads.
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+ * Check for 16-byte alignment, taking into consideration the
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+ * alignment that has already been checked.
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*/
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- if (h.aa.align < MO_128) {
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- /*
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- * TODO: align should be MO_64, so we only need test bit 3,
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- * which means we could use TBNZ instead of ANDS+B_C.
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- */
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- tcg_out_logicali(s, Ilogic_imm_ANDSI, 0, TCG_REG_XZR, addr_reg,
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- 15);
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- branch = s->code_ptr;
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- tcg_out_insn(s, bcond_imm, B_C, TCG_COND_NE, 0);
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+ int a_mask = 16 - (1 << h.aa.align);
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+
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+ if (a_mask > 0) {
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+ label = gen_new_label();
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+ tgen_brcondi(s, TCG_TYPE_I32, TCG_COND_TSTNE,
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+ addr_reg, a_mask, label);
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use_pair = true;
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}
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@@ -1971,7 +1966,7 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
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if (use_pair) {
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/* "b .+8", branching across the one insn of use_pair. */
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tcg_out_insn(s, branch, B, 2);
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- reloc_pc19(branch, tcg_splitwx_to_rx(s->code_ptr));
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+ tcg_out_label(s, label);
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}
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}
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