target/riscv: Support raising misaligned exceptions for scalar loads/stores
When the Zicclsm extension is not enabled, raise misaligned load/store exceptions for misaligned accesses from scalar load/store instructions. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Max Chou <max.chou@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260810055618.1175500-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang committed
Aug 10, 2026 at 13:56 UTC
7ff17f127bbf08bb17d2754d43028bab79a1c709
1 file changed
+6
target/riscv/tcg/insn_trans/trans_rvi.c.inc
+6
@@ -413,6 +413,9 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
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if (ctx->cfg_ptr->ext_zama16b) {
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memop |= MO_ATOM_WITHIN16;
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}
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+ if (!ctx->cfg_ptr->ext_zicclsm) {
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+ memop |= MO_ALIGN;
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+ }
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decode_save_opc(ctx, 0);
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if (get_xl(ctx) == MXL_RV128) {
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out = gen_load_i128(ctx, a, memop);
@@ -524,6 +527,9 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
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if (ctx->cfg_ptr->ext_zama16b) {
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memop |= MO_ATOM_WITHIN16;
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}
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+ if (!ctx->cfg_ptr->ext_zicclsm) {
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+ memop |= MO_ALIGN;
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+ }
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decode_save_opc(ctx, 0);
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if (get_xl(ctx) == MXL_RV128) {
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return gen_store_i128(ctx, a, memop);