hw/ssi/aspeed_smc: Convert mem ops to read/write_with_attrs for error handling
Error conditions (invalid flash mode, unwritable flash) now return MEMTX_ERROR instead of silently succeeding or returning undefined values. This allows the memory subsystem to properly propagate transaction errors to the guest, improving QEMU reliability. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3335 Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20260323125545.577653-2-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Cédric Le Goater committed
Mar 23, 2026 at 13:55 UTC
80c5be945877ea3f258679c6042df8f0efd77202
1 file changed
+28
-21
hw/ssi/aspeed_smc.c
+28
-21
@@ -493,17 +493,18 @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
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}
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}
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-static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
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+static MemTxResult aspeed_smc_flash_read(void *opaque, hwaddr addr,
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+ uint64_t *data, unsigned size, MemTxAttrs attrs)
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{
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AspeedSMCFlash *fl = opaque;
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AspeedSMCState *s = fl->controller;
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- uint64_t ret = 0;
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int i;
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+ *data = 0;
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switch (aspeed_smc_flash_mode(fl)) {
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case CTRL_USERMODE:
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for (i = 0; i < size; i++) {
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- ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i);
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+ *data |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i);
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}
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break;
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case CTRL_READMODE:
@@ -512,18 +513,19 @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
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aspeed_smc_flash_setup(fl, addr);
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for (i = 0; i < size; i++) {
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- ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i);
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+ *data |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i);
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}
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aspeed_smc_flash_unselect(fl);
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break;
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default:
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aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl));
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+ return MEMTX_ERROR;
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}
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- trace_aspeed_smc_flash_read(fl->cs, addr, size, ret,
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+ trace_aspeed_smc_flash_read(fl->cs, addr, size, *data,
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aspeed_smc_flash_mode(fl));
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- return ret;
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+ return MEMTX_OK;
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}
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/*
@@ -624,8 +626,8 @@ static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
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return false;
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}
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-static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
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- unsigned size)
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+static MemTxResult aspeed_smc_flash_write(void *opaque, hwaddr addr,
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+ uint64_t data, unsigned size, MemTxAttrs attrs)
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{
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AspeedSMCFlash *fl = opaque;
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AspeedSMCState *s = fl->controller;
@@ -636,7 +638,7 @@ static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
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if (!aspeed_smc_is_writable(fl)) {
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aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr);
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- return;
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+ return MEMTX_ERROR;
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}
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switch (aspeed_smc_flash_mode(fl)) {
@@ -661,12 +663,15 @@ static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
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break;
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default:
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aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl));
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+ return MEMTX_ERROR;
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}
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+
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+ return MEMTX_OK;
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}
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static const MemoryRegionOps aspeed_smc_flash_ops = {
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- .read = aspeed_smc_flash_read,
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- .write = aspeed_smc_flash_write,
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+ .read_with_attrs = aspeed_smc_flash_read,
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+ .write_with_attrs = aspeed_smc_flash_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
@@ -754,7 +759,8 @@ static void aspeed_smc_reset(DeviceState *d)
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s->snoop_dummies = 0;
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}
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-static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
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+static MemTxResult aspeed_smc_read(void *opaque, hwaddr addr, uint64_t *data,
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+ unsigned int size, MemTxAttrs attrs)
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{
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AspeedSMCState *s = ASPEED_SMC(opaque);
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AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(opaque);
@@ -782,12 +788,13 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
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trace_aspeed_smc_read(addr << 2, size, s->regs[addr]);
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- return s->regs[addr];
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+ *data = s->regs[addr];
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} else {
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qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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- return -1;
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+ *data = -1;
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}
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+ return MEMTX_OK;
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}
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static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask)
@@ -1108,8 +1115,8 @@ static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl)
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s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
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}
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1111
-static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
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- unsigned int size)
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+static MemTxResult aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
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+ unsigned int size, MemTxAttrs attrs)
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{
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AspeedSMCState *s = ASPEED_SMC(opaque);
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AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
@@ -1159,13 +1166,13 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
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} else {
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qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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- return;
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}
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+ return MEMTX_OK;
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}
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static const MemoryRegionOps aspeed_smc_ops = {
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- .read = aspeed_smc_read,
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- .write = aspeed_smc_write,
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+ .read_with_attrs = aspeed_smc_read,
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+ .write_with_attrs = aspeed_smc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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@@ -2007,8 +2014,8 @@ static const uint32_t aspeed_2700_fmc_resets[ASPEED_SMC_R_MAX] = {
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};
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static const MemoryRegionOps aspeed_2700_smc_flash_ops = {
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- .read = aspeed_smc_flash_read,
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- .write = aspeed_smc_flash_write,
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+ .read_with_attrs = aspeed_smc_flash_read,
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+ .write_with_attrs = aspeed_smc_flash_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,