hw/i3c/dw-i3c: Use 32 bits on MMIO writes
The registers are only 32 bits wide, so we should cast the 64-bit value passed in to only be 32 bits wide. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-12-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Feb 25, 2026 at 02:12 UTC
8141dc29457d2e7d2350992cac7e53dc6f775c6d
1 file changed
+3
-2
hw/i3c/dw-i3c.c
+3
-2
@@ -363,10 +363,11 @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value,
363
{
364
DWI3C *s = DW_I3C(opaque);
365
uint32_t addr = offset >> 2;
366
+ uint32_t val32 = (uint32_t)value;
367
368
trace_dw_i3c_write(s->id, offset, value);
369
369
- value &= ~dw_i3c_ro[addr];
370
+ val32 &= ~dw_i3c_ro[addr];
371
switch (addr) {
372
case R_HW_CAPABILITY:
373
case R_RESPONSE_QUEUE_PORT:
@@ -392,7 +393,7 @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value,
393
case R_RESET_CTRL:
394
break;
395
default:
395
- s->regs[addr] = value;
396
+ s->regs[addr] = val32;
397
break;
398
}
399
}