@samitouri / QOSamiQemu / commits / 820552a92e

target/riscv/cpu: add CPU unrealize callback

Next patch is going to dynamically allocate debug trigger arrays during realize() time. We need a way of freeing them during unrealize(), which doesn't exist at this moment. There's a lot going on in that patch already so we're adding the callback infrastructure beforehand. Suggested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260617131710.1855353-2-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Daniel Henrique Barboza committed Jun 17, 2026 at 10:17 UTC 820552a92e32cb15c0dda0e2d82563c056a0283a

2 files changed +11

target/riscv/cpu.c

@@ -1009,6 +1009,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)

1009 mcc->parent_realize(dev, errp);

1010 }

1011

1012 +static void riscv_cpu_unrealize(DeviceState *dev)

1013 +{

1014 + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);

1015 +

1016 + mcc->parent_unrealize(dev);

1017 +}

1018 +

1019 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu)

1020 {

1021 if (tcg_enabled()) {

@@ -2664,6 +2671,8 @@ static void riscv_cpu_common_class_init(ObjectClass *c, const void *data)

2671

2672 device_class_set_parent_realize(dc, riscv_cpu_realize,

2673 &mcc->parent_realize);

2674 + device_class_set_parent_unrealize(dc, riscv_cpu_unrealize,

2675 + &mcc->parent_unrealize);

2676

2677 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,

2678 &mcc->parent_phases);

target/riscv/cpu.h

@@ -576,6 +576,7 @@ typedef struct RISCVCPUDef {

576 /**

577 * RISCVCPUClass:

578 * @parent_realize: The parent class' realize handler.

579 + * @parent_unrealize: The parent class' unrealize handler.

580 * @parent_phases: The parent class' reset phase handlers.

581 *

582 * A RISCV CPU model.

@@ -584,6 +585,7 @@ struct RISCVCPUClass {

585 CPUClass parent_class;

586

587 DeviceRealize parent_realize;

588 + DeviceUnrealize parent_unrealize;

589 ResettablePhases parent_phases;

590 RISCVCPUDef *def;

591 };