target/arm: Implement SME BFSCALE
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260826174213.614571-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 26, 2026 at 10:41 UTC
822e87ec4a85f7016ad4bbdb1fc37944e3c7decc
5 files changed
+27
-4
target/arm/cpu-features.h
+5
@@ -1877,6 +1877,11 @@ static inline bool isar_feature_aa64_sme_tmop_f8f32(const ARMISARegisters *id)
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return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_f8f32(id);
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}
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+static inline bool isar_feature_aa64_sme2_sve_bfscale(const ARMISARegisters *id)
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+{
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+ return isar_feature_aa64_sme2(id) && isar_feature_aa64_sve_bfscale(id);
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+}
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+
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/*
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* Feature tests for "does this exist in either 32-bit or 64-bit?"
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*/
target/arm/tcg/helper-a64-defs.h
+1
@@ -151,6 +151,7 @@ DEF_HELPER_FLAGS_5(gvec_famin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32
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DEF_HELPER_FLAGS_5(gvec_famax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_5(gvec_famin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(gvec_fscale_b16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_5(gvec_fscale_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_5(gvec_fscale_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_5(gvec_fscale_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
target/arm/tcg/sme.decode
+16
-4
@@ -287,8 +287,14 @@ ADD_n1 1100000 1 .. 10 .... 1010.0 11000 .... 0 @z2z_4x1
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SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_2x1
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SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_4x1
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-FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_2x1
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-FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_4x1
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+{
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+ BFSCALE_n1 1100000 1 00 10 .... 1010.0 01100 .... 0 @z2z_2x1_e0
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+ FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_2x1
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+}
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+{
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+ BFSCALE_n1 1100000 1 00 10 .... 1010.0 01100 .... 0 @z2z_4x1_e0
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+ FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_4x1
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+}
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FMUL_n1 1100000 1 esz:2 1 zm:4 0 111010 ....0 ....0 \
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&zzz_en n=2 zd=%zd_ax2 zn=%zn_ax2
@@ -365,8 +371,14 @@ FAMAX_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 0 @z2z_4x4
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FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_2x2
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FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_4x4
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-FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_2x2
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-FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_4x4
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+{
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+ BFSCALE_nn 1100000 1 00 1 ..... 1011.0 01100 .... 0 @z2z_2x2_e0
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+ FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_2x2
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+}
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+{
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+ BFSCALE_nn 1100000 1 00 1 ..... 1011.0 01100 .... 0 @z2z_4x4_e0
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+ FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_4x4
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+}
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FMUL_nn 1100000 1 esz:2 1 ....0 111001 ....0 ....0 \
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&zzz_en n=2 zd=%zd_ax2 zn=%zn_ax2 zm=%zm_ax2
target/arm/tcg/translate-sme.c
+4
@@ -890,6 +890,10 @@ static gen_helper_gvec_3_ptr * const f_vector_fscale[4] = {
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};
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TRANS_FEAT(FSCALE_n1, aa64_sme2_f8cvt, do_zzz_n1_fpst, a, f_vector_fscale[a->esz])
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TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_zzz_nn_fpst, a, f_vector_fscale[a->esz])
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+TRANS_FEAT(BFSCALE_n1, aa64_sme2_sve_bfscale, do_zzz_n1_fpst, a,
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+ gen_helper_gvec_fscale_b16)
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+TRANS_FEAT(BFSCALE_nn, aa64_sme2_sve_bfscale, do_zzz_nn_fpst, a,
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+ gen_helper_gvec_fscale_b16)
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static gen_helper_gvec_3_ptr * const f_vector_fmul[4] = {
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NULL,
target/arm/tcg/vec_helper64.c
+1
@@ -179,6 +179,7 @@ DO_3OP(gvec_famin_s, float32_famin, float32)
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DO_3OP(gvec_famax_d, float64_famax, float64)
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DO_3OP(gvec_famin_d, float64_famin, float64)
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+DO_3OP(gvec_fscale_b16, bfloat16_scalbn, int16_t)
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DO_3OP(gvec_fscale_h, float16_scalbn, int16_t)
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DO_3OP(gvec_fscale_s, float32_scalbn, int32_t)
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DO_3OP(gvec_fscale_d, scalbn_d, int64_t)