hw/net/xilinx_axienet: Fix PHY register 17 link status reporting
The Marvell 88E1111 PHY register 17 (PHY Specific Status Register) bit 10 reports real-time link status. Previously, this register returned a fixed value of 0x8800 with bit 10 always cleared, causing U-Boot to always detect "No link" even when the link was up. Signed-off-by: Jay Chang <jay.chang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20260713064617.85374-1-jay.chang@sifive.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Jay Chang committed
Jul 20, 2026 at 19:05 UTC
83927347227c91dd659e7ed718d656ed0d551ab6
1 file changed
+3
hw/net/xilinx_axienet.c
+3
@@ -103,6 +103,9 @@ static unsigned int tdk_read(struct PHY *phy, unsigned int req)
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case 17:
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/* Marvell PHY on many xilinx boards. */
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r = 0x8000; /* 1000Mb */
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+ if (phy->link) {
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+ r |= 0x0400; /* Link is up */
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+ }
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break;
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case 18:
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{