hw/i3c/aspeed_i3c: Add register RO field masks
Adds read-only register masks for the Aspeed I3C controller registers. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-9-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Feb 25, 2026 at 02:12 UTC
84001254ecbcd892fca5d0d529a856a121e36da3
1 file changed
+16
hw/i3c/aspeed_i3c.c
+16
@@ -74,6 +74,21 @@ REG32(I3C6_REG1, 0x64)
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FIELD(I3C6_REG1, SA_EN, 15, 1)
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FIELD(I3C6_REG1, INST_ID, 16, 4)
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+static const uint32_t ast2600_i3c_controller_ro[ASPEED_I3C_NR_REGS] = {
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+ [R_I3C1_REG0] = 0xcc000000,
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+ [R_I3C1_REG1] = 0xfff00000,
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+ [R_I3C2_REG0] = 0xcc000000,
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+ [R_I3C2_REG1] = 0xfff00000,
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+ [R_I3C3_REG0] = 0xcc000000,
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+ [R_I3C3_REG1] = 0xfff00000,
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+ [R_I3C4_REG0] = 0xcc000000,
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+ [R_I3C4_REG1] = 0xfff00000,
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+ [R_I3C5_REG0] = 0xcc000000,
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+ [R_I3C5_REG1] = 0xfff00000,
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+ [R_I3C6_REG0] = 0xcc000000,
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+ [R_I3C6_REG1] = 0xfff00000,
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+};
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+
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static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size)
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{
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AspeedI3CState *s = ASPEED_I3C(opaque);
@@ -97,6 +112,7 @@ static void aspeed_i3c_write(void *opaque,
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addr >>= 2;
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+ data &= ~ast2600_i3c_controller_ro[addr];
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/* I3C controller register */
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switch (addr) {
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case R_I3C1_REG1: