target/arm: Implement BFMOP4 (non-widening)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260702204314.79224-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jul 2, 2026 at 13:43 UTC
84294be165d77e465d371c4c5fd621a84a085dfe
5 files changed
+60
target/arm/cpu-features.h
+5
@@ -1807,6 +1807,11 @@ isar_feature_aa64_sme_f16f16_or_f8f16(const ARMISARegisters *id)
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return isar_feature_aa64_sme_f16f16(id) || isar_feature_aa64_sme_f8f16(id);
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}
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+static inline bool isar_feature_aa64_sme_mop4_b16b16(const ARMISARegisters *id)
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+{
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+ return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_b16b16(id);
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+}
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+
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static inline bool isar_feature_aa64_sme_mop4_f16f16(const ARMISARegisters *id)
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{
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return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_f16f16(id);
target/arm/tcg/helper-sme-defs.h
+4
@@ -367,3 +367,7 @@ DEF_HELPER_FLAGS_5(sme_ah_fmop4s_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst,
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DEF_HELPER_FLAGS_5(sme_fmop4a_dd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_5(sme_fmop4s_dd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_5(sme_ah_fmop4s_dd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+
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+DEF_HELPER_FLAGS_5(sme_bfmop4a_hh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(sme_bfmop4s_hh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(sme_ah_bfmop4s_hh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
target/arm/tcg/sme.decode
+1
@@ -1101,6 +1101,7 @@ LUTI4_s_4b 1100 0000 1001 101 1 00 00 00 ....0 zd:5 \
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@mop4_o3 .... .... ... m:1 .... .... .. n:1 ... . s:1 . zad:3 \
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&mop4 zm=%mop4_zm zn=%mop4_zn
1103
1104
+BFMOP4_hh 1000 0001 001. ...0 0000 00.. ..0. 100. @mop4_o1
1105
FMOP4_hh 1000 0001 000. ...0 0000 00.. ..0. 100. @mop4_o1
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FMOP4_ss 1000 0000 000. ...0 0000 00.. ..0. 00.. @mop4_o2
1107
FMOP4_dd 1000 0000 110. ...0 0000 00.. ..0. 1... @mop4_o3
target/arm/tcg/sme_helper.c
+42
@@ -2761,3 +2761,45 @@ void HELPER(sme_ah_fmop4s_dd)(void *vza, void *vzn, void *vzm,
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{
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sme_mop4(vza, vzn, vzm, fpst, desc, sizeof(float64), inner_ah_fmop4s_dd);
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}
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+
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+static void inner_bfmop4a_hh(void *vd, void *vn, void *vm, void *vinfo)
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+{
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+ bfloat16 *d = vd, *n = vn, *m = vm;
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+ float_status *fpst = vinfo;
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+
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+ *d = bfloat16_muladd(*n, *m, *d, 0, fpst);
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+}
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+
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+void HELPER(sme_bfmop4a_hh)(void *vza, void *vzn, void *vzm,
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+ float_status *fpst, uint32_t desc)
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+{
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+ sme_mop4(vza, vzn, vzm, fpst, desc, sizeof(bfloat16), inner_bfmop4a_hh);
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+}
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+
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+static void inner_bfmop4s_hh(void *vd, void *vn, void *vm, void *vinfo)
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+{
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+ bfloat16 *d = vd, *n = vn, *m = vm;
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+ float_status *fpst = vinfo;
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+
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+ *d = bfloat16_muladd(bfloat16_chs(*n), *m, *d, 0, fpst);
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+}
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+
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+void HELPER(sme_bfmop4s_hh)(void *vza, void *vzn, void *vzm,
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+ float_status *fpst, uint32_t desc)
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+{
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+ sme_mop4(vza, vzn, vzm, fpst, desc, sizeof(bfloat16), inner_bfmop4s_hh);
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+}
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+
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+static void inner_ah_bfmop4s_hh(void *vd, void *vn, void *vm, void *vinfo)
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+{
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+ bfloat16 *d = vd, *n = vn, *m = vm;
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+ float_status *fpst = vinfo;
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+
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+ *d = bfloat16_muladd(*n, *m, *d, float_muladd_negate_product, fpst);
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+}
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+
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+void HELPER(sme_ah_bfmop4s_hh)(void *vza, void *vzn, void *vzm,
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+ float_status *fpst, uint32_t desc)
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+{
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+ sme_mop4(vza, vzn, vzm, fpst, desc, sizeof(bfloat16), inner_ah_bfmop4s_hh);
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+}
target/arm/tcg/translate-sme.c
+8
@@ -2025,6 +2025,14 @@ static bool do_mop4_fp(DisasContext *s, arg_mop4 *a, MemOp esz,
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return true;
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}
2027
2028
+static gen_helper_gvec_3_ptr * const bfmop4_hh[3] = {
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+ gen_helper_sme_bfmop4a_hh,
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+ gen_helper_sme_bfmop4s_hh,
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+ gen_helper_sme_ah_bfmop4s_hh
2032
+};
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+TRANS_FEAT(BFMOP4_hh, aa64_sme_mop4_b16b16,
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+ do_mop4_fp, a, MO_16, FPST_ZA, bfmop4_hh)
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+
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static gen_helper_gvec_3_ptr * const fmop4_hh[3] = {
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gen_helper_sme_fmop4a_hh,
2038
gen_helper_sme_fmop4s_hh,