target/arm: Enable FEAT_SVE2p2 and FEAT_SME2p2 for -cpu max
These features are tied together if both SVE and SME are enabled. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260826174213.614571-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 26, 2026 at 10:41 UTC
85d508c1fc2d50ec9d7e859a8d5db7a8d3738911
3 files changed
+7
-2
docs/system/arm/emulation.rst
+2
@@ -180,6 +180,7 @@ the following architecture extensions:
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- FEAT_SME (Scalable Matrix Extension)
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- FEAT_SME2 (Scalable Matrix Extension version 2)
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- FEAT_SME2p1 (Scalable Matrix Extension version 2.1)
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+- FEAT_SME2p2 (Scalable Matrix Extension version 2.2)
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- FEAT_SME_B16B16 (Non-widening BFloat16 arithmetic for SME2)
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- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
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- FEAT_SME_F16F16 (Non-widening half-precision FP16 arithmetic for SME2)
@@ -204,6 +205,7 @@ the following architecture extensions:
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- FEAT_SVE_SM4 (Scalable Vector SM4 instructions)
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- FEAT_SVE2 (Scalable Vector Extension version 2)
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- FEAT_SVE2p1 (Scalable Vector Extension version 2.1)
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+- FEAT_SVE2p2 (Scalable Vector Extension version 2.2)
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- FEAT_SPECRES (Speculation restriction instructions)
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- FEAT_SSBS (Speculative Store Bypass Safe)
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- FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2)
linux-user/aarch64/elfload.c
+2
@@ -178,6 +178,8 @@ abi_ulong get_elf_hwcap(CPUState *cs)
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GET_FEATURE_ID(aa64_fprcvt, ARM_HWCAP_A64_FPRCVT);
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GET_FEATURE_ID(aa64_sme_mop4, ARM_HWCAP_A64_SME_SMOP4);
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GET_FEATURE_ID(aa64_sme_tmop, ARM_HWCAP_A64_SME_STMOP);
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+ GET_FEATURE_ID(aa64_sve2p2, ARM_HWCAP_A64_SVE2P2);
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+ GET_FEATURE_ID(aa64_sme2p2, ARM_HWCAP_A64_SME2P2);
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return hwcaps;
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}
target/arm/tcg/cpu64.c
+3
-2
@@ -1470,8 +1470,9 @@ void aarch64_max_v9_tcg_initfn(Object *obj)
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SET_IDREG(isar, ID_AA64MMFR4, t);
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t = GET_IDREG(isar, ID_AA64ZFR0);
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- t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* v9.2: FEAT_SVE2p1 */
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+ t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 3); /* v9.4: FEAT_SVE2p2 */
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t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMULL128 */
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+ t = FIELD_DP64(t, ID_AA64ZFR0, ELTPERM, 1); /* v9.4: FEAT_SVE2p2 */
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t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitPerm */
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t = FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* v9.2: FEAT_SVE_B16B16 */
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t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3 */
@@ -1498,7 +1499,7 @@ void aarch64_max_v9_tcg_initfn(Object *obj)
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t = FIELD_DP64(t, ID_AA64SMFR0, I16I32, 5); /* v9.2: FEAT_SME2 */
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t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* v9.2: FEAT_SME_F64F64 */
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t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* v9.2: FEAT_SME_I16I64 */
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- t = FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 2); /* v9.2: FEAT_SME2p1 */
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+ t = FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 3); /* v9.4: FEAT_SME2p2 */
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t = FIELD_DP64(t, ID_AA64SMFR0, LUTv2, 1); /* v9.2: FEAT_SME_LUTv2 */
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t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* v9.2: FEAT_SME_FA64 */
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SET_IDREG(isar, ID_AA64SMFR0, t);