hw/i2c/aspeed_i2c: Increase AST2700 buffer mode size and adjust offset
Update the AST2700 I2C buffer mode configuration to match the latest firmware definition: - Increase buffer mode pool size from 0x20 to 0x40 - Adjust buffer mode base offset to 0x1c0 Since the buffer mode region size changes, the migration state layout is also modified. Bump the VMState version numbers to prevent incompatible migration between old and new machine states. Fixes: 1809ab6a67359e0876981cd05d2a50b2843eabad ("hw/i2c/aspeed: Add AST2700 support") Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260603040027.938816-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Jun 3, 2026 at 04:00 UTC
86210448ca1ad4cba2939f6d1c4388dcef885534
2 files changed
+24
-24
hw/i2c/aspeed_i2c.c
+23
-23
@@ -1132,8 +1132,8 @@ static const MemoryRegionOps aspeed_i2c_bus_pool_ops = {
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static const VMStateDescription aspeed_i2c_bus_vmstate = {
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.name = TYPE_ASPEED_I2C,
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- .version_id = 7,
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- .minimum_version_id = 6,
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+ .version_id = 8,
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+ .minimum_version_id = 8,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AspeedI2CBus, ASPEED_I2C_NEW_NUM_REG),
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VMSTATE_UINT32_V(pending_intr_sts, AspeedI2CBus, 7),
@@ -1145,8 +1145,8 @@ static const VMStateDescription aspeed_i2c_bus_vmstate = {
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static const VMStateDescription aspeed_i2c_vmstate = {
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.name = TYPE_ASPEED_I2C,
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- .version_id = 3,
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- .minimum_version_id = 3,
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+ .version_id = 4,
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+ .minimum_version_id = 4,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32(intr_status, AspeedI2CState),
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VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState,
@@ -1250,37 +1250,37 @@ static void aspeed_i2c_instance_init(Object *obj)
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* Address Definitions (AST2700)
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* 0x000 ... 0x0FF: Global Register
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* 0x100 ... 0x19F: Device 0
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- * 0x1A0 ... 0x1BF: Device 0 buffer
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+ * 0x1C0 ... 0x1FF: Device 0 buffer
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* 0x200 ... 0x29F: Device 1
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- * 0x2A0 ... 0x2BF: Device 1 buffer
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+ * 0x2C0 ... 0x2FF: Device 1 buffer
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* 0x300 ... 0x39F: Device 2
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- * 0x3A0 ... 0x3BF: Device 2 buffer
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+ * 0x3C0 ... 0x3FF: Device 2 buffer
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* 0x400 ... 0x49F: Device 3
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- * 0x4A0 ... 0x4BF: Device 3 buffer
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+ * 0x4C0 ... 0x4FF: Device 3 buffer
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* 0x500 ... 0x59F: Device 4
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- * 0x5A0 ... 0x5BF: Device 4 buffer
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+ * 0x5C0 ... 0x5FF: Device 4 buffer
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* 0x600 ... 0x69F: Device 5
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- * 0x6A0 ... 0x6BF: Device 5 buffer
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+ * 0x6C0 ... 0x6FF: Device 5 buffer
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* 0x700 ... 0x79F: Device 6
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- * 0x7A0 ... 0x7BF: Device 6 buffer
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+ * 0x7C0 ... 0x7FF: Device 6 buffer
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* 0x800 ... 0x89F: Device 7
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- * 0x8A0 ... 0x8BF: Device 7 buffer
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+ * 0x8C0 ... 0x8FF: Device 7 buffer
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* 0x900 ... 0x99F: Device 8
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- * 0x9A0 ... 0x9BF: Device 8 buffer
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+ * 0x9C0 ... 0x9FF: Device 8 buffer
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* 0xA00 ... 0xA9F: Device 9
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- * 0xAA0 ... 0xABF: Device 9 buffer
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+ * 0xAC0 ... 0xAFF: Device 9 buffer
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* 0xB00 ... 0xB9F: Device 10
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- * 0xBA0 ... 0xBBF: Device 10 buffer
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+ * 0xBC0 ... 0xBFF: Device 10 buffer
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* 0xC00 ... 0xC9F: Device 11
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- * 0xCA0 ... 0xCBF: Device 11 buffer
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+ * 0xCC0 ... 0xCFF: Device 11 buffer
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* 0xD00 ... 0xD9F: Device 12
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- * 0xDA0 ... 0xDBF: Device 12 buffer
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+ * 0xDC0 ... 0xDFF: Device 12 buffer
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* 0xE00 ... 0xE9F: Device 13
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- * 0xEA0 ... 0xEBF: Device 13 buffer
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+ * 0xEC0 ... 0xEFF: Device 13 buffer
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* 0xF00 ... 0xF9F: Device 14
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- * 0xFA0 ... 0xFBF: Device 14 buffer
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+ * 0xFC0 ... 0xFFF: Device 14 buffer
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* 0x1000 ... 0x109F: Device 15
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- * 0x10A0 ... 0x10BF: Device 15 buffer
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+ * 0x10C0 ... 0x10BF: Device 15 buffer
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*/
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static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
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{
@@ -1666,9 +1666,9 @@ static void aspeed_2700_i2c_class_init(ObjectClass *klass, const void *data)
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aic->reg_gap_size = 0x60;
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aic->gap = -1; /* no gap */
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aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq;
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- aic->pool_size = 0x20;
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- aic->pool_gap_size = 0xe0;
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- aic->pool_base = 0x1a0;
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+ aic->pool_size = 0x40;
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+ aic->pool_gap_size = 0xc0;
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+ aic->pool_base = 0x1c0;
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aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base;
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aic->has_dma = true;
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aic->mem_size = 0x2000;
include/hw/i2c/aspeed_i2c.h
+1
-1
@@ -35,7 +35,7 @@ OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
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#define ASPEED_I2C_NR_BUSSES 16
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#define ASPEED_I2C_SHARE_POOL_SIZE 0x800
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-#define ASPEED_I2C_BUS_POOL_SIZE 0x20
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+#define ASPEED_I2C_BUS_POOL_SIZE 0x40
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#define ASPEED_I2C_NEW_NUM_REG (0xa0 >> 2)
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#define A_I2CD_M_STOP_CMD BIT(5)