tests/tcg: add test for MTE FAR
This functionality was previously enabled but not advertised or tested. This commit adds a new test, mte-9, that tests the code for proper full-address reporting. FEAT_MTE_TAGGED_FAR requires that FAR_ELx report the full logical address, including tag bits. Signed-off-by: Gabriel Brookman <brookmangabriel@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260529-feat-mte4-v7-14-ccbd3c14eb3c@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gabriel Brookman committed
May 29, 2026 at 12:52 UTC
869e1cdec89682f29e5a04ea701137be82ba0758
2 files changed
+49
-1
tests/tcg/aarch64/Makefile.target
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@@ -64,7 +64,7 @@ AARCH64_TESTS += bti-2
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# MTE Tests
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ifneq ($(CROSS_CC_HAS_ARMV8_MTE),)
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-AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7 mte-8
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+AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7 mte-8 mte-9
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mte-%: CFLAGS += $(CROSS_CC_HAS_ARMV8_MTE)
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endif
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tests/tcg/aarch64/mte-9.c
new
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@@ -0,0 +1,48 @@
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+/*
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+ * Memory tagging, full-address reporting.
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+ *
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+ * Copyright (c) 2021 Linaro Ltd
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "mte.h"
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+
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+static void *faulting_ptr;
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+
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+void pass(int sig, siginfo_t *info, void *uc)
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+{
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+ assert(faulting_ptr == info->si_addr);
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+ exit(0);
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+}
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+
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+int main(int ac, char **av)
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+{
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+ struct sigaction sa;
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+ int *p0, *p1, *p2;
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+ long excl = 1;
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+
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+ enable_mte(PR_MTE_TCF_SYNC);
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+ p0 = alloc_mte_mem(sizeof(*p0));
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+
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+ /* Create two differently tagged pointers. */
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+ asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl));
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+ asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1));
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+ assert(excl != 1);
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+ asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl));
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+ assert(p1 != p2);
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+
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+ /* Store the tag from the first pointer. */
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+ asm("stg %0, [%0]" : : "r"(p1));
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+
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+ *p1 = 0;
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+
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+ memset(&sa, 0, sizeof(sa));
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+ sa.sa_sigaction = pass;
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+ sa.sa_flags = SA_SIGINFO;
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+ sigaction(SIGSEGV, &sa, NULL);
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+
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+ faulting_ptr = p2;
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+ *p2 = 0;
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+
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+ abort();
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+}