disas/riscv: Simplify c.addi
While c.addi with imm == 0 and rd == 0 is c.nop, other c.addi with imm == 0 and rd != 0 are not illegal, but are reserved as HINTs. Go ahead and disassemble as c.addi rather than falling back to invalid. Further, there's no reason to differentiate c.nop, since we have c.addi -> addi -> nop vs c.nop -> addi -> nop via decompress and pseudo translation steps. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260812223142.349142-15-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Richard Henderson committed
Aug 12, 2026 at 15:31 UTC
87f162e424d2622732b82749594f57271af7b3af
1 file changed
+3
-8
disas/riscv.c
+3
-8
@@ -263,7 +263,6 @@ typedef enum {
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rv_op_c_fsd = 231,
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rv_op_c_sw = 232,
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rv_op_c_fsw = 233,
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- rv_op_c_nop = 234,
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rv_op_c_addi = 235,
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rv_op_c_jal = 236,
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rv_op_c_li = 237,
@@ -1896,10 +1895,9 @@ static const rv_opcode_data rvi_opcode_data[] = {
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{ "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw,
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rv_op_sw },
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{ "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
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- { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi,
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- rv_op_addi },
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+ { },
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{ "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
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- rv_op_addi, rvcd_imm_nz },
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+ rv_op_addi },
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{ "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
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{ "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
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rv_op_addi },
@@ -3010,10 +3008,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 1:
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switch ((inst >> 13) & 0b111) {
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case 0:
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- switch ((inst >> 2) & 0b11111111111) {
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- case 0: op = rv_op_c_nop; break;
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- default: op = rv_op_c_addi; break;
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- }
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+ op = rv_op_c_addi; /* or unspecified HINT */
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break;
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case 1:
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if (isa == rv32) {