hw/riscv/riscv-iommu.c: set RISCV_IOMMU_FQ_HDR_PV appropriately
We're hardcoding 'true' to FQ_HDR_PV in riscv_iommu_report_fault(). Use the 'pv' bool the caller provides that indicates if the process_id is valid. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3556 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260626173341.3661446-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
Jun 26, 2026 at 14:33 UTC
887d2d75b1a9da8d8252d9f983558c45173afbae
1 file changed
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-1
hw/riscv/riscv-iommu.c
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@@ -580,7 +580,7 @@ static void riscv_iommu_report_fault(RISCVIOMMUState *s,
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ev.hdr = set_field(ev.hdr, RISCV_IOMMU_FQ_HDR_CAUSE, cause);
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ev.hdr = set_field(ev.hdr, RISCV_IOMMU_FQ_HDR_TTYPE, fault_type);
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ev.hdr = set_field(ev.hdr, RISCV_IOMMU_FQ_HDR_DID, ctx->devid);
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- ev.hdr = set_field(ev.hdr, RISCV_IOMMU_FQ_HDR_PV, true);
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+ ev.hdr = set_field(ev.hdr, RISCV_IOMMU_FQ_HDR_PV, pv);
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if (pv) {
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ev.hdr = set_field(ev.hdr, RISCV_IOMMU_FQ_HDR_PID, ctx->process_id);