target/arm: Implement FSCALE for AdvSIMD
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260522220306.235200-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
May 22, 2026 at 15:02 UTC
891388a9dd5e5459e64ba3acc23c3f3cf716f670
6 files changed
+24
-6
target/arm/tcg/a64.decode
+3
@@ -1198,6 +1198,9 @@ FAMAX 0.00 1110 1.1 ..... 11011 1 ..... ..... @qrrr_sd
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FAMIN 0.10 1110 110 ..... 00011 1 ..... ..... @qrrr_h
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FAMIN 0.10 1110 1.1 ..... 11011 1 ..... ..... @qrrr_sd
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+FSCALE 0.10 1110 110 ..... 00111 1 ..... ..... @qrrr_h
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+FSCALE 0.10 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd
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+
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### Advanced SIMD scalar x indexed element
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FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
target/arm/tcg/helper-a64-defs.h
+4
@@ -152,6 +152,10 @@ DEF_HELPER_FLAGS_5(gvec_famin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32
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DEF_HELPER_FLAGS_5(gvec_famax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_5(gvec_famin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(gvec_fscale_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(gvec_fscale_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(gvec_fscale_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+
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#ifndef CONFIG_USER_ONLY
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DEF_HELPER_2(exception_return, void, env, i64)
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#endif
target/arm/tcg/sve_helper.c
-6
@@ -4736,12 +4736,6 @@ DO_ZPZZ_FP(sve_ah_fabd_h, uint16_t, H1_2, ah_abd_h)
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DO_ZPZZ_FP(sve_ah_fabd_s, uint32_t, H1_4, ah_abd_s)
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DO_ZPZZ_FP(sve_ah_fabd_d, uint64_t, H1_8, ah_abd_d)
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-static inline float64 scalbn_d(float64 a, int64_t b, float_status *s)
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-{
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- int b_int = MIN(MAX(b, INT_MIN), INT_MAX);
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- return float64_scalbn(a, b_int, s);
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-}
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-
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DO_ZPZZ_FP(sve_fscalbn_h, int16_t, H1_2, float16_scalbn)
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DO_ZPZZ_FP(sve_fscalbn_s, int32_t, H1_4, float32_scalbn)
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DO_ZPZZ_FP(sve_fscalbn_d, int64_t, H1_8, scalbn_d)
target/arm/tcg/translate-a64.c
+7
@@ -6493,6 +6493,13 @@ static gen_helper_gvec_3_ptr * const f_vector_famin[3] = {
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};
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TRANS_FEAT(FAMIN, aa64_faminmax, do_fp3_vector, a, 0, f_vector_famin)
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+static gen_helper_gvec_3_ptr * const f_vector_fscale[3] = {
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+ gen_helper_gvec_fscale_h,
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+ gen_helper_gvec_fscale_s,
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+ gen_helper_gvec_fscale_d,
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+};
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+TRANS_FEAT(FSCALE, aa64_f8cvt, do_fp3_vector, a, 0, f_vector_fscale)
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+
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static bool do_fmlal(DisasContext *s, arg_qrrr_e *a, bool is_s, bool is_2)
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{
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if (fp_access_check(s)) {
target/arm/tcg/vec_helper64.c
+4
@@ -178,3 +178,7 @@ DO_3OP(gvec_famax_s, float32_famax, float32)
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DO_3OP(gvec_famin_s, float32_famin, float32)
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DO_3OP(gvec_famax_d, float64_famax, float64)
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DO_3OP(gvec_famin_d, float64_famin, float64)
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+
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+DO_3OP(gvec_fscale_h, float16_scalbn, int16_t)
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+DO_3OP(gvec_fscale_s, float32_scalbn, int32_t)
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+DO_3OP(gvec_fscale_d, scalbn_d, int64_t)
target/arm/tcg/vec_internal.h
+6
@@ -349,6 +349,12 @@ float32 float32_famin(float32, float32, float_status *);
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float64 float64_famax(float64, float64, float_status *);
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float64 float64_famin(float64, float64, float_status *);
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+static inline float64 scalbn_d(float64 a, int64_t b, float_status *s)
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+{
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+ int b_int = MIN(MAX(b, INT_MIN), INT_MAX);
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+ return float64_scalbn(a, b_int, s);
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+}
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+
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/*
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* Decode helper functions for predicate as counter.
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*/