@samitouri / QOSamiQemu / commits / 8a34849f5b

hw/riscv/riscv-iommu: rename regs_rw to regs

The existing nomenclature can be misleading: regs_rw can cosplay as 'read and write' mask, in particular because we have regs_ro which is a read only mask. regs_rw is the current reg value, and all bits that aren't on the regs_ro mask is considered r/w bits. Rename regs_rw to 'regs' to be on par with the nomenclature other devices uses (e.g. cadence_gem). Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260625210833.3294437-2-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Daniel Henrique Barboza committed Jun 25, 2026 at 18:08 UTC 8a34849f5ba4f52a183c4ce21317ab9e832889a3

3 files changed +35 -31

hw/riscv/riscv-iommu-hpm.c

+2 -2

@@ -60,8 +60,8 @@ static void hpm_incr_ctr(RISCVIOMMUState *s, uint32_t ctr_idx)

60 const uint32_t off = ctr_idx << 3;

61 uint64_t cntr_val;

63 - cntr_val = ldq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off]);

64 - stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off], cntr_val + 1);

63 + cntr_val = ldq_le_p(&s->regs[RISCV_IOMMU_REG_IOHPMCTR_BASE + off]);

64 + stq_le_p(&s->regs[RISCV_IOMMU_REG_IOHPMCTR_BASE + off], cntr_val + 1);

66 trace_riscv_iommu_hpm_incr_ctr(cntr_val);

hw/riscv/riscv-iommu.c

+18 -18

@@ -2034,8 +2034,8 @@ static void riscv_iommu_process_cq_control(RISCVIOMMUState *s)

2034 s->cq_mask = (2ULL << get_field(base, RISCV_IOMMU_CQB_LOG2SZ)) - 1;

2035 s->cq_addr = PPN_PHYS(get_field(base, RISCV_IOMMU_CQB_PPN));

2036 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_CQT], ~s->cq_mask);

2037 - stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_CQH], 0);

2038 - stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_CQT], 0);

2037 + stl_le_p(&s->regs[RISCV_IOMMU_REG_CQH], 0);

2038 + stl_le_p(&s->regs[RISCV_IOMMU_REG_CQT], 0);

2039 ctrl_set = RISCV_IOMMU_CQCSR_CQON;

2040 ctrl_clr = RISCV_IOMMU_CQCSR_BUSY | RISCV_IOMMU_CQCSR_CQMF |

2041 RISCV_IOMMU_CQCSR_CMD_ILL | RISCV_IOMMU_CQCSR_CMD_TO |

@@ -2075,8 +2075,8 @@ static void riscv_iommu_process_fq_control(RISCVIOMMUState *s)

2075 s->fq_mask = (2ULL << get_field(base, RISCV_IOMMU_FQB_LOG2SZ)) - 1;

2076 s->fq_addr = PPN_PHYS(get_field(base, RISCV_IOMMU_FQB_PPN));

2077 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_FQH], ~s->fq_mask);

2078 - stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_FQH], 0);

2079 - stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_FQT], 0);

2078 + stl_le_p(&s->regs[RISCV_IOMMU_REG_FQH], 0);

2079 + stl_le_p(&s->regs[RISCV_IOMMU_REG_FQT], 0);

2080 ctrl_set = RISCV_IOMMU_FQCSR_FQON;

2081 ctrl_clr = RISCV_IOMMU_FQCSR_BUSY | RISCV_IOMMU_FQCSR_FQMF |

2082 RISCV_IOMMU_FQCSR_FQOF;

@@ -2105,8 +2105,8 @@ static void riscv_iommu_process_pq_control(RISCVIOMMUState *s)

2105 s->pq_mask = (2ULL << get_field(base, RISCV_IOMMU_PQB_LOG2SZ)) - 1;

2106 s->pq_addr = PPN_PHYS(get_field(base, RISCV_IOMMU_PQB_PPN));

2107 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_PQH], ~s->pq_mask);

2108 - stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_PQH], 0);

2109 - stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_PQT], 0);

2108 + stl_le_p(&s->regs[RISCV_IOMMU_REG_PQH], 0);

2109 + stl_le_p(&s->regs[RISCV_IOMMU_REG_PQT], 0);

2110 ctrl_set = RISCV_IOMMU_PQCSR_PQON;

2111 ctrl_clr = RISCV_IOMMU_PQCSR_BUSY | RISCV_IOMMU_PQCSR_PQMF |

2112 RISCV_IOMMU_PQCSR_PQOF;

@@ -2276,9 +2276,9 @@ static void riscv_iommu_write_reg_val(RISCVIOMMUState *s,

2276 {

2277 uint64_t ro = ldn_le_p(&s->regs_ro[reg_addr], size);

2278 uint64_t wc = ldn_le_p(&s->regs_wc[reg_addr], size);

2279 - uint64_t rw = ldn_le_p(&s->regs_rw[reg_addr], size);

2279 + uint64_t curr_val = ldn_le_p(&s->regs[reg_addr], size);

2280

2281 - stn_le_p(dest, size, ((rw & ro) | (data & ~ro)) & ~(data & wc));

2281 + stn_le_p(dest, size, ((curr_val & ro) | (data & ~ro)) & ~(data & wc));

2282 }

2283

2284 static MemTxResult riscv_iommu_mmio_write(void *opaque, hwaddr addr,

@@ -2378,12 +2378,12 @@ static MemTxResult riscv_iommu_mmio_write(void *opaque, hwaddr addr,

2378 * is set IOMMU behavior of additional writes to the register

2379 * is UNSPECIFIED.

2380 */

2381 - riscv_iommu_write_reg_val(s, &s->regs_rw[addr], addr, size, data);

2381 + riscv_iommu_write_reg_val(s, &s->regs[addr], addr, size, data);

2382

2383 /* Busy flag update, MSB 4-byte register. */

2384 if (busy) {

2385 - uint32_t rw = ldl_le_p(&s->regs_rw[regb]);

2386 - stl_le_p(&s->regs_rw[regb], rw | busy);

2385 + uint32_t rw = ldl_le_p(&s->regs[regb]);

2386 + stl_le_p(&s->regs[regb], rw | busy);

2387 }

2388

2389 /* Process HPM writes and update any internal state if needed. */

@@ -2428,13 +2428,13 @@ static MemTxResult riscv_iommu_mmio_read(void *opaque, hwaddr addr,

2428 * it's not dependent over the timer callback and is computed

2429 * from cycle overflow.

2430 */

2431 - val = ldq_le_p(&s->regs_rw[addr]);

2431 + val = ldq_le_p(&s->regs[addr]);

2432 val |= (riscv_iommu_hpmcycle_read(s) & RISCV_IOMMU_IOHPMCYCLES_OVF)

2433 ? RISCV_IOMMU_IOCOUNTOVF_CY

2434 : 0;

2435 ptr = (uint8_t *)&val + (addr & 3);

2436 } else {

2437 - ptr = &s->regs_rw[addr];

2437 + ptr = &s->regs[addr];

2438 }

2439

2440 val = ldn_le_p(ptr, size);

@@ -2529,7 +2529,7 @@ static void riscv_iommu_instance_init(Object *obj)

2529 s->cap |= RISCV_IOMMU_CAP_PD8;

2530

2531 /* register storage */

2532 - s->regs_rw = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);

2532 + s->regs = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);

2533 s->regs_ro = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);

2534 s->regs_wc = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);

2535

@@ -2554,7 +2554,7 @@ static void riscv_iommu_instance_finalize(Object *obj)

2554 {

2555 RISCVIOMMUState *s = RISCV_IOMMU(obj);

2556

2557 - g_free(s->regs_rw);

2557 + g_free(s->regs);

2558 g_free(s->regs_ro);

2559 g_free(s->regs_wc);

2560

@@ -2608,8 +2608,8 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)

2608 "riscv-iommu-regs", RISCV_IOMMU_REG_SIZE);

2609

2610 /* Set power-on register state */

2611 - stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_CAP], s->cap);

2612 - stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_FCTL], 0);

2611 + stq_le_p(&s->regs[RISCV_IOMMU_REG_CAP], s->cap);

2612 + stq_le_p(&s->regs[RISCV_IOMMU_REG_FCTL], 0);

2613 stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_FCTL],

2614 ~(RISCV_IOMMU_FCTL_BE | RISCV_IOMMU_FCTL_WSI));

2615 stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_DDTP],

@@ -2634,7 +2634,7 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)

2634 RISCV_IOMMU_PQCSR_BUSY);

2635 stl_le_p(&s->regs_wc[RISCV_IOMMU_REG_IPSR], ~0);

2636 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_ICVEC], 0);

2637 - stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_DDTP], s->ddtp);

2637 + stq_le_p(&s->regs[RISCV_IOMMU_REG_DDTP], s->ddtp);

2638 /* If debug registers enabled. */

2639 if (s->cap & RISCV_IOMMU_CAP_DBG) {

2640 stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_TR_REQ_IOVA], 0);

hw/riscv/riscv-iommu.h

+15 -11

@@ -76,9 +76,13 @@ struct RISCVIOMMUState {

77 /* MMIO Hardware Interface */

78 MemoryRegion regs_mr;

79 - uint8_t *regs_rw; /* register state (user write) */

79 + uint8_t *regs; /* current register state */

80 uint8_t *regs_wc; /* write-1-to-clear mask */

81 - uint8_t *regs_ro; /* read-only mask */

81 + /*

82 + * read-only mask. NOTE: bits not present in this RO

83 + * mask are assumed to be read and write.

84 + */

85 + uint8_t *regs_ro;

87 QLIST_ENTRY(RISCVIOMMUState) iommus;

88 QLIST_HEAD(, RISCVIOMMUSpace) spaces;

@@ -120,39 +124,39 @@ struct RISCVIOMMUContext {

124 static inline uint32_t riscv_iommu_reg_mod32(RISCVIOMMUState *s,

125 unsigned idx, uint32_t set, uint32_t clr)

126 {

123 - uint32_t val = ldl_le_p(s->regs_rw + idx);

124 - stl_le_p(s->regs_rw + idx, (val & ~clr) | set);

127 + uint32_t val = ldl_le_p(s->regs + idx);

128 + stl_le_p(s->regs + idx, (val & ~clr) | set);

129 return val;

130 }

131

132 static inline void riscv_iommu_reg_set32(RISCVIOMMUState *s, unsigned idx,

133 uint32_t set)

134 {

131 - stl_le_p(s->regs_rw + idx, set);

135 + stl_le_p(s->regs + idx, set);

136 }

137

138 static inline uint32_t riscv_iommu_reg_get32(RISCVIOMMUState *s, unsigned idx)

139 {

136 - return ldl_le_p(s->regs_rw + idx);

140 + return ldl_le_p(s->regs + idx);

141 }

142

143 static inline uint64_t riscv_iommu_reg_mod64(RISCVIOMMUState *s, unsigned idx,

144 uint64_t set, uint64_t clr)

145 {

142 - uint64_t val = ldq_le_p(s->regs_rw + idx);

143 - stq_le_p(s->regs_rw + idx, (val & ~clr) | set);

146 + uint64_t val = ldq_le_p(s->regs + idx);

147 + stq_le_p(s->regs + idx, (val & ~clr) | set);

148 return val;

149 }

150

151 static inline void riscv_iommu_reg_set64(RISCVIOMMUState *s, unsigned idx,

152 uint64_t set)

153 {

150 - stq_le_p(s->regs_rw + idx, set);

154 + stq_le_p(s->regs + idx, set);

155 }

156

157 static inline uint64_t riscv_iommu_reg_get64(RISCVIOMMUState *s,

154 - unsigned idx)

158 + unsigned idx)

159 {

156 - return ldq_le_p(s->regs_rw + idx);

160 + return ldq_le_p(s->regs + idx);

161 }

162 #endif