target/arm: Enable FEAT_SME_TMOP for -cpu max
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260713230244.70174-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 11, 2026 at 20:14 UTC
8ae365bdc8395e54fe0e137143858b505409d82a
3 files changed
+4
-1
docs/system/arm/emulation.rst
+1
@@ -188,6 +188,7 @@ the following architecture extensions:
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- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
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- FEAT_SME_LUTv2 (Lookup table instructions with 4-bit indices and 8-bit elements)
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- FEAT_SME_MOP4 (Quarter-tile outer product instructions)
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+- FEAT_SME_TMOP (Structured sparsity outer product instructions)
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- FEAT_SSVE_AES (Streaming SVE Mode Advanced Encryption Standard and 128-bit polynomial multiply long instructions)
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- FEAT_SSVE_FEXPA (Streaming FEXPA instruction)
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- FEAT_SSVE_FP8DOT2 (SVE2 FP8 2-way dot product to half-precision instructions in Streaming SVE mode)
linux-user/aarch64/elfload.c
+1
@@ -177,6 +177,7 @@ abi_ulong get_elf_hwcap(CPUState *cs)
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GET_FEATURE_ID(aa64_ssve_fexpa, ARM_HWCAP_A64_SME_SFEXPA);
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GET_FEATURE_ID(aa64_fprcvt, ARM_HWCAP_A64_FPRCVT);
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GET_FEATURE_ID(aa64_sme_mop4, ARM_HWCAP_A64_SME_SMOP4);
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+ GET_FEATURE_ID(aa64_sme_tmop, ARM_HWCAP_A64_SME_STMOP);
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return hwcaps;
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}
target/arm/tcg/cpu64.c
+2
-1
@@ -1384,8 +1384,9 @@ void aarch64_max_tcg_initfn(Object *obj)
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SET_IDREG(isar, ID_AA64DFR0, t);
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t = GET_IDREG(isar, ID_AA64SMFR0);
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- t = FIELD_DP64(t, ID_AA64SMFR0, SFEXPA, 1); /* FEAT_SSVE_FEXPA */
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t = FIELD_DP64(t, ID_AA64SMFR0, SMOP4, 1); /* FEAT_SME_MOP4 */
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+ t = FIELD_DP64(t, ID_AA64SMFR0, STMOP, 1); /* FEAT_SME_TMOP */
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+ t = FIELD_DP64(t, ID_AA64SMFR0, SFEXPA, 1); /* FEAT_SSVE_FEXPA */
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t = FIELD_DP64(t, ID_AA64SMFR0, AES, 1); /* FEAT_SSVE_AES */
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t = FIELD_DP64(t, ID_AA64SMFR0, SF8DP2, 1); /* FEAT_SSVE_FP8DOT2 */
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t = FIELD_DP64(t, ID_AA64SMFR0, SF8DP4, 1); /* FEAT_SSVE_FP8DOT4 */