target/mips: Expand octeon reflections inline
Use tcg_gen_revbit64_i64 instead of out-of-line helpers. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson committed
Jul 30, 2026 at 12:04 UTC
8b416699c88f78c56eb668b18d40876034857542
3 files changed
+43
-48
target/mips/helper.h
-7
@@ -27,10 +27,6 @@ DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
27
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/* Octeon COP2 selector operation helpers. */
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DEF_HELPER_1(octeon_cp2_mf_crc_iv_reflect, i64, env)
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-DEF_HELPER_1(octeon_cp2_mf_gfm_mul_reflect0, i64, env)
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-DEF_HELPER_1(octeon_cp2_mf_gfm_mul_reflect1, i64, env)
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-DEF_HELPER_1(octeon_cp2_mf_gfm_resinp_reflect0, i64, env)
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-DEF_HELPER_1(octeon_cp2_mf_gfm_resinp_reflect1, i64, env)
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DEF_HELPER_2(octeon_cp2_mt_crc_write_iv_reflect, void, env, i64)
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DEF_HELPER_2(octeon_cp2_mt_crc_write_polynomial_reflect, void, env, i64)
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DEF_HELPER_2(octeon_cp2_mt_crc_write_byte, void, env, i64)
@@ -43,9 +39,6 @@ DEF_HELPER_2(octeon_cp2_mt_crc_write_dword, void, env, i64)
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DEF_HELPER_2(octeon_cp2_mt_crc_write_var, void, env, i64)
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DEF_HELPER_2(octeon_cp2_mt_crc_write_dword_reflect, void, env, i64)
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DEF_HELPER_2(octeon_cp2_mt_crc_write_var_reflect, void, env, i64)
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-DEF_HELPER_2(octeon_cp2_mt_gfm_mul_reflect0, void, env, i64)
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-DEF_HELPER_2(octeon_cp2_mt_gfm_mul_reflect1, void, env, i64)
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-DEF_HELPER_2(octeon_cp2_mt_gfm_xor0_reflect, void, env, i64)
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DEF_HELPER_2(octeon_cp2_mt_gfm_xormul1_reflect, void, env, i64)
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DEF_HELPER_2(octeon_cp2_mt_gfm_xormul1, void, env, i64)
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DEF_HELPER_1(octeon_cp2_mt_sha3_startop, void, env)
target/mips/tcg/octeon_crypto.c
-35
@@ -2127,41 +2127,6 @@ uint64_t helper_octeon_cp2_mf_crc_iv_reflect(CPUMIPSState *env)
2127
return octeon_crc_reflect32_by_byte(env->octeon_crypto.crc_iv);
2128
}
2129
2130
-uint64_t helper_octeon_cp2_mf_gfm_mul_reflect0(CPUMIPSState *env)
2131
-{
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- return revbit64(env->octeon_crypto.gfm_mul[0]);
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-}
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-
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-uint64_t helper_octeon_cp2_mf_gfm_mul_reflect1(CPUMIPSState *env)
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-{
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- return revbit64(env->octeon_crypto.gfm_mul[1]);
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-}
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-
2140
-uint64_t helper_octeon_cp2_mf_gfm_resinp_reflect0(CPUMIPSState *env)
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-{
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- return revbit64(env->octeon_crypto.gfm_resinp[0]);
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-}
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-
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-uint64_t helper_octeon_cp2_mf_gfm_resinp_reflect1(CPUMIPSState *env)
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-{
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- return revbit64(env->octeon_crypto.gfm_resinp[1]);
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-}
2149
-
2150
-void helper_octeon_cp2_mt_gfm_mul_reflect0(CPUMIPSState *env, uint64_t value)
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-{
2152
- env->octeon_crypto.gfm_mul[0] = revbit64(value);
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-}
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-
2155
-void helper_octeon_cp2_mt_gfm_mul_reflect1(CPUMIPSState *env, uint64_t value)
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-{
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- env->octeon_crypto.gfm_mul[1] = revbit64(value);
2158
-}
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-
2160
-void helper_octeon_cp2_mt_gfm_xor0_reflect(CPUMIPSState *env, uint64_t value)
2161
-{
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- env->octeon_crypto.gfm_resinp[0] ^= revbit64(value);
2163
-}
2164
-
2130
static void octeon_gfm_xormul1_common(MIPSOcteonCryptoState *crypto,
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uint64_t value)
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{
target/mips/tcg/octeon_translate.c
+43
-6
@@ -28,6 +28,8 @@
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TRANS(NAME, trans_octeon_cp2_mf_hsh_pair, \
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OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX)]), \
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OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX) + 1]))
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+#define CP2_MF_REFLECT(NAME, FIELD) \
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+ TRANS(NAME, trans_octeon_cp2_mf_reflect, OCTEON_CRYPTO_OFFSET(FIELD))
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#define CP2_MF_HELPER(NAME, SUFFIX) \
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TRANS(NAME, trans_octeon_cp2_mf_helper, \
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gen_helper_octeon_cp2_mf_ ## SUFFIX)
@@ -44,6 +46,8 @@
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TRANS(NAME, trans_octeon_cp2_mt_hsh_pair, \
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OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX)]), \
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OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX) + 1]))
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+#define CP2_MT_REFLECT(NAME, FIELD) \
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+ TRANS(NAME, trans_octeon_cp2_mt_reflect, OCTEON_CRYPTO_OFFSET(FIELD))
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#define CP2_MT_HELPER(NAME, SUFFIX) \
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TRANS(NAME, trans_octeon_cp2_mt_helper, \
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gen_helper_octeon_cp2_mt_ ## SUFFIX)
@@ -110,6 +114,17 @@ static bool trans_octeon_cp2_mf_hsh_pair(DisasContext *ctx, arg_cp2 *a,
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return true;
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}
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+static bool trans_octeon_cp2_mf_reflect(DisasContext *ctx, arg_cp2 *a,
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+ int offset)
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+{
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+ TCGv_i64 value = tcg_temp_new_i64();
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+
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+ tcg_gen_ld_i64(value, tcg_env, offset);
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+ tcg_gen_revbit64_i64(value, value);
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+ gen_store_gpr(value, a->rt);
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+ return true;
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+}
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+
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static bool trans_octeon_cp2_mf_helper(DisasContext *ctx, arg_cp2 *a,
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void (*gen_helper)(TCGv_i64, TCGv_env))
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{
@@ -183,6 +198,17 @@ static bool trans_octeon_cp2_mt_xor_i64(DisasContext *ctx, arg_cp2 *a,
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return true;
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}
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+static bool trans_octeon_cp2_mt_reflect(DisasContext *ctx, arg_cp2 *a,
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+ int offset)
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+{
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+ TCGv_i64 value = tcg_temp_new_i64();
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+
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+ gen_load_gpr(value, a->rt);
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+ tcg_gen_revbit64_i64(value, value);
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+ tcg_gen_st_i64(value, tcg_env, offset);
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+ return true;
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+}
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+
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static bool trans_octeon_cp2_mt_helper(DisasContext *ctx, arg_cp2 *a,
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void (*gen_helper)(TCGv_env, TCGv_i64))
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{
@@ -200,6 +226,17 @@ static bool trans_octeon_cp2_mt_helper_env(DisasContext *ctx, arg_cp2 *a,
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return true;
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}
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+static void gen_helper_octeon_cp2_mt_gfm_xor0_reflect(TCGv_env t_env,
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+ TCGv_i64 value)
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+{
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+ TCGv_i64 resinp = tcg_temp_new_i64();
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+
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+ tcg_gen_revbit64_i64(value, value);
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+ tcg_gen_ld_i64(resinp, t_env, OCTEON_CRYPTO_OFFSET(gfm_resinp[0]));
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+ tcg_gen_xor_i64(resinp, resinp, value);
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+ tcg_gen_st_i64(resinp, t_env, OCTEON_CRYPTO_OFFSET(gfm_resinp[0]));
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+}
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+
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CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT0, hsh_dat, 0);
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CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT1, hsh_dat, 1);
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CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT2, hsh_dat, 2);
@@ -241,10 +278,10 @@ CP2_MF_I64(CVM_MF_LLM_DATA1, llm_data[1]);
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CP2_MF_HELPER(CVM_MF_CRC_IV_REFLECT, crc_iv_reflect);
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CP2_MF_I64(CVM_MF_SHA3_DAT24, sha3_dat24);
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-CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT0, gfm_mul_reflect0);
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-CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT1, gfm_mul_reflect1);
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-CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT0, gfm_resinp_reflect0);
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-CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT1, gfm_resinp_reflect1);
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+CP2_MF_REFLECT(CVM_MF_GFM_MUL_REFLECT0, gfm_mul[0])
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+CP2_MF_REFLECT(CVM_MF_GFM_MUL_REFLECT1, gfm_mul[1])
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+CP2_MF_REFLECT(CVM_MF_GFM_RESINP_REFLECT0, gfm_resinp[0])
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+CP2_MF_REFLECT(CVM_MF_GFM_RESINP_REFLECT1, gfm_resinp[1])
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CP2_MF_I64(CVM_MF_HSH_DATW0, hsh_dat[0]);
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CP2_MF_I64(CVM_MF_HSH_DATW1, hsh_dat[1]);
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CP2_MF_I64(CVM_MF_HSH_DATW2, hsh_dat[2]);
@@ -281,8 +318,8 @@ CP2_MT_HSH_PAIR(CVM_MT_HSH_IV0, hsh_iv, 0);
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CP2_MT_HSH_PAIR(CVM_MT_HSH_IV1, hsh_iv, 1);
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CP2_MT_HSH_PAIR(CVM_MT_HSH_IV2, hsh_iv, 2);
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CP2_MT_HSH_PAIR(CVM_MT_HSH_IV3, hsh_iv, 3);
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-CP2_MT_HELPER(CVM_MT_GFM_MUL_REFLECT0, gfm_mul_reflect0);
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-CP2_MT_HELPER(CVM_MT_GFM_MUL_REFLECT1, gfm_mul_reflect1);
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+CP2_MT_REFLECT(CVM_MT_GFM_MUL_REFLECT0, gfm_mul[0]);
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+CP2_MT_REFLECT(CVM_MT_GFM_MUL_REFLECT1, gfm_mul[1]);
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CP2_MT_HELPER(CVM_MT_GFM_XOR0_REFLECT, gfm_xor0_reflect);
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CP2_MT_I64(CVM_MT_3DES_KEY0, des3_key[0]);
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CP2_MT_I64(CVM_MT_3DES_KEY1, des3_key[1]);