@samitouri / QOSamiQemu / commits / 8b529eeccb

hw/arm/aspeed_ast27x0: Set EHCI ctrldssegment-default

On AST2700 platforms, system DRAM is mapped above 4GB with a base address at 0x400000000. The Linux EHCI driver programs the segment register to zero when 64-bit addressing is supported. As a result, descriptor addresses derived from the EHCI registers do not include the DRAM base address. Descriptor memory is allocated through the DMA API with a 64-bit DMA mask, allowing descriptors to reside in DRAM above 4GB. On AST2700, EHCI queue heads (QH) and queue element transfer descriptors (qTD) are therefore placed at addresses starting from 0x400000000. Set the ctrldssegment-default property to "sc->memmap[ASPEED_DEV_SDRAM] >> 32" so the upper 32 bits of descriptor addresses are adjusted accordingly. This allows the emulated EHCI controller to construct correct system addresses when accessing descriptors in DRAM above 4GB. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/qemu-devel/20260713032704.3583103-9-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>

Jamin Lin committed Jul 13, 2026 at 03:27 UTC 8b529eeccbe05b616da5ee86dc980038807c3a06

1 file changed +3

hw/arm/aspeed_ast27x0.c

@@ -870,6 +870,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)

870

871 /* EHCI */

872 for (i = 0; i < sc->ehcis_num; i++) {

873 + object_property_set_int(OBJECT(&s->ehci[i]), "ctrldssegment-default",

874 + sc->memmap[ASPEED_DEV_SDRAM] >> 32,

875 + &error_abort);

876 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {

877 return;

878 }