target/arm: Split decode of BFloat SME FMAX/FMIN
Split decode so that feature detection can be handled external to do_zzz_{n1,nn}_fpst. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260826174213.614571-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 26, 2026 at 10:41 UTC
8c0bcee43ab30aac67b0f7ca1fce04babb8ceb54
3 files changed
+115
-45
target/arm/cpu-features.h
+5
@@ -1748,6 +1748,11 @@ static inline bool isar_feature_aa64_sme2p2_or_sve2p2(const ARMISARegisters *id)
1748
return isar_feature_aa64_sme2p2(id) || isar_feature_aa64_sve2p2(id);
1749
}
1750
1751
+static inline bool isar_feature_aa64_sme2_sve_b16b16(const ARMISARegisters *id)
1752
+{
1753
+ return isar_feature_aa64_sme2(id) && isar_feature_aa64_sve_b16b16(id);
1754
+}
1755
+
1756
static inline bool isar_feature_aa64_sme2_i16i64(const ARMISARegisters *id)
1757
{
1758
return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_i16i64(id);
target/arm/tcg/sme.decode
+74
-16
@@ -227,6 +227,11 @@ UMOPA2_s 1010000 1 10 0 ..... ... ... ..... . 10 .. @op_32
227
@z2z_4x1 ....... . esz:2 .. zm:4 ....1. ..... ...0 . \
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&zzz_en n=4 zd=%zd_ax4 zn=%zd_ax4
229
230
+@z2z_2x1_e0 ....... . .. .. zm:4 ....0. ..... .... . \
231
+ &zzz_en esz=0 n=2 zd=%zd_ax2 zn=%zd_ax2
232
+@z2z_4x1_e0 ....... . .. .. zm:4 ....1. ..... ...0 . \
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+ &zzz_en esz=0 n=4 zd=%zd_ax4 zn=%zd_ax4
234
+
235
SMAX_n1 1100000 1 .. 10 .... 1010.0 00000 .... 0 @z2z_2x1
236
SMAX_n1 1100000 1 .. 10 .... 1010.0 00000 .... 0 @z2z_4x1
237
UMAX_n1 1100000 1 .. 10 .... 1010.0 00000 .... 1 @z2z_2x1
@@ -236,14 +241,38 @@ SMIN_n1 1100000 1 .. 10 .... 1010.0 00001 .... 0 @z2z_4x1
241
UMIN_n1 1100000 1 .. 10 .... 1010.0 00001 .... 1 @z2z_2x1
242
UMIN_n1 1100000 1 .. 10 .... 1010.0 00001 .... 1 @z2z_4x1
243
239
-FMAX_n1 1100000 1 .. 10 .... 1010.0 01000 .... 0 @z2z_2x1
240
-FMAX_n1 1100000 1 .. 10 .... 1010.0 01000 .... 0 @z2z_4x1
241
-FMIN_n1 1100000 1 .. 10 .... 1010.0 01000 .... 1 @z2z_2x1
242
-FMIN_n1 1100000 1 .. 10 .... 1010.0 01000 .... 1 @z2z_4x1
243
-FMAXNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 0 @z2z_2x1
244
-FMAXNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 0 @z2z_4x1
245
-FMINNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 1 @z2z_2x1
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-FMINNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 1 @z2z_4x1
244
+{
245
+ BFMAX_n1 1100000 1 00 10 .... 1010.0 01000 .... 0 @z2z_2x1_e0
246
+ FMAX_n1 1100000 1 .. 10 .... 1010.0 01000 .... 0 @z2z_2x1
247
+}
248
+{
249
+ BFMAX_n1 1100000 1 00 10 .... 1010.0 01000 .... 0 @z2z_4x1_e0
250
+ FMAX_n1 1100000 1 .. 10 .... 1010.0 01000 .... 0 @z2z_4x1
251
+}
252
+{
253
+ BFMIN_n1 1100000 1 00 10 .... 1010.0 01000 .... 1 @z2z_2x1_e0
254
+ FMIN_n1 1100000 1 .. 10 .... 1010.0 01000 .... 1 @z2z_2x1
255
+}
256
+{
257
+ BFMIN_n1 1100000 1 00 10 .... 1010.0 01000 .... 1 @z2z_4x1_e0
258
+ FMIN_n1 1100000 1 .. 10 .... 1010.0 01000 .... 1 @z2z_4x1
259
+}
260
+{
261
+ BFMAXNM_n1 1100000 1 00 10 .... 1010.0 01001 .... 0 @z2z_2x1_e0
262
+ FMAXNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 0 @z2z_2x1
263
+}
264
+{
265
+ BFMAXNM_n1 1100000 1 00 10 .... 1010.0 01001 .... 0 @z2z_4x1_e0
266
+ FMAXNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 0 @z2z_4x1
267
+}
268
+{
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+ BFMINNM_n1 1100000 1 00 10 .... 1010.0 01001 .... 1 @z2z_2x1_e0
270
+ FMINNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 1 @z2z_2x1
271
+}
272
+{
273
+ BFMINNM_n1 1100000 1 00 10 .... 1010.0 01001 .... 1 @z2z_4x1_e0
274
+ FMINNM_n1 1100000 1 .. 10 .... 1010.0 01001 .... 1 @z2z_4x1
275
+}
276
277
SRSHL_n1 1100000 1 .. 10 .... 1010.0 10001 .... 0 @z2z_2x1
278
SRSHL_n1 1100000 1 .. 10 .... 1010.0 10001 .... 0 @z2z_4x1
@@ -269,6 +298,11 @@ FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_4x1
298
@z2z_4x4 ....... . esz:2 . ...00 ....1. ..... ...0 . \
299
&zzz_en n=4 zd=%zd_ax4 zn=%zd_ax4 zm=%zm_ax4
300
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+@z2z_2x2_e0 ....... . .. . ....0 ....0. ..... .... . \
302
+ &zzz_en esz=0 n=2 zd=%zd_ax2 zn=%zd_ax2 zm=%zm_ax2
303
+@z2z_4x4_e0 ....... . .. . ...00 ....1. ..... ...0 . \
304
+ &zzz_en esz=0 n=4 zd=%zd_ax4 zn=%zd_ax4 zm=%zm_ax4
305
+
306
SMAX_nn 1100000 1 .. 1 ..... 1011.0 00000 .... 0 @z2z_2x2
307
SMAX_nn 1100000 1 .. 1 ..... 1011.0 00000 .... 0 @z2z_4x4
308
UMAX_nn 1100000 1 .. 1 ..... 1011.0 00000 .... 1 @z2z_2x2
@@ -278,14 +312,38 @@ SMIN_nn 1100000 1 .. 1 ..... 1011.0 00001 .... 0 @z2z_4x4
312
UMIN_nn 1100000 1 .. 1 ..... 1011.0 00001 .... 1 @z2z_2x2
313
UMIN_nn 1100000 1 .. 1 ..... 1011.0 00001 .... 1 @z2z_4x4
314
281
-FMAX_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 0 @z2z_2x2
282
-FMAX_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 0 @z2z_4x4
283
-FMIN_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 1 @z2z_2x2
284
-FMIN_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 1 @z2z_4x4
285
-FMAXNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 0 @z2z_2x2
286
-FMAXNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 0 @z2z_4x4
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-FMINNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 1 @z2z_2x2
288
-FMINNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 1 @z2z_4x4
315
+{
316
+ BFMAX_nn 1100000 1 00 1 ..... 1011.0 01000 .... 0 @z2z_2x2_e0
317
+ FMAX_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 0 @z2z_2x2
318
+}
319
+{
320
+ BFMAX_nn 1100000 1 00 1 ..... 1011.0 01000 .... 0 @z2z_4x4_e0
321
+ FMAX_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 0 @z2z_4x4
322
+}
323
+{
324
+ BFMIN_nn 1100000 1 00 1 ..... 1011.0 01000 .... 1 @z2z_2x2_e0
325
+ FMIN_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 1 @z2z_2x2
326
+}
327
+{
328
+ BFMIN_nn 1100000 1 00 1 ..... 1011.0 01000 .... 1 @z2z_4x4_e0
329
+ FMIN_nn 1100000 1 .. 1 ..... 1011.0 01000 .... 1 @z2z_4x4
330
+}
331
+{
332
+ BFMAXNM_nn 1100000 1 00 1 ..... 1011.0 01001 .... 0 @z2z_2x2_e0
333
+ FMAXNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 0 @z2z_2x2
334
+}
335
+{
336
+ BFMAXNM_nn 1100000 1 00 1 ..... 1011.0 01001 .... 0 @z2z_4x4_e0
337
+ FMAXNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 0 @z2z_4x4
338
+}
339
+{
340
+ BFMINNM_nn 1100000 1 00 1 ..... 1011.0 01001 .... 1 @z2z_2x2_e0
341
+ FMINNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 1 @z2z_2x2
342
+}
343
+{
344
+ BFMINNM_nn 1100000 1 00 1 ..... 1011.0 01001 .... 1 @z2z_4x4_e0
345
+ FMINNM_nn 1100000 1 .. 1 ..... 1011.0 01001 .... 1 @z2z_4x4
346
+}
347
348
SRSHL_nn 1100000 1 .. 1 ..... 1011.0 10001 .... 0 @z2z_2x2
349
SRSHL_nn 1100000 1 .. 1 ..... 1011.0 10001 .... 0 @z2z_4x4
target/arm/tcg/translate-sme.c
+36
-29
@@ -747,20 +747,15 @@ TRANS_FEAT(URSHL_nn, aa64_sme2, do_zzz_nn, a, gen_sme2_urshl)
747
TRANS_FEAT(SQDMULH_nn, aa64_sme2, do_zzz_nn, a, gen_gvec_sve2_sqdmulh)
748
749
static bool do_zzz_n1_fpst(DisasContext *s, arg_zzz_en *a,
750
- gen_helper_gvec_3_ptr * const fns[4])
750
+ gen_helper_gvec_3_ptr *fn)
751
{
752
int esz = a->esz, vsz, mofs;
753
int overlap = -1;
754
- gen_helper_gvec_3_ptr *fn = fns[esz];
754
TCGv_ptr fpst;
755
756
if (fn == NULL) {
757
return false;
758
}
760
- /* These insns use MO_8 to encode BFloat16. */
761
- if (esz == MO_8 && !dc_isar_feature(aa64_sve_b16b16, s)) {
762
- return false;
763
- }
759
if (!sme_sm_enabled_check(s)) {
760
return true;
761
}
@@ -786,18 +781,14 @@ static bool do_zzz_n1_fpst(DisasContext *s, arg_zzz_en *a,
781
}
782
783
static bool do_zzz_nn_fpst(DisasContext *s, arg_zzz_en *a,
789
- gen_helper_gvec_3_ptr * const fns[4])
784
+ gen_helper_gvec_3_ptr *fn)
785
{
786
int esz = a->esz, vsz;
792
- gen_helper_gvec_3_ptr *fn = fns[esz];
787
TCGv_ptr fpst;
788
789
if (fn == NULL) {
790
return false;
791
}
798
- if (esz == MO_8 && !dc_isar_feature(aa64_sve_b16b16, s)) {
799
- return false;
800
- }
792
if (!sme_sm_enabled_check(s)) {
793
return true;
794
}
@@ -816,48 +807,64 @@ static bool do_zzz_nn_fpst(DisasContext *s, arg_zzz_en *a,
807
}
808
809
static gen_helper_gvec_3_ptr * const f_vector_fmax[2][4] = {
819
- { gen_helper_gvec_fmax_b16,
810
+ { NULL,
811
gen_helper_gvec_fmax_h,
812
gen_helper_gvec_fmax_s,
813
gen_helper_gvec_fmax_d },
823
- { gen_helper_gvec_ah_fmax_b16,
814
+ { NULL,
815
gen_helper_gvec_ah_fmax_h,
816
gen_helper_gvec_ah_fmax_s,
817
gen_helper_gvec_ah_fmax_d },
818
};
828
-TRANS_FEAT(FMAX_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmax[s->fpcr_ah])
829
-TRANS_FEAT(FMAX_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmax[s->fpcr_ah])
819
+TRANS_FEAT(FMAX_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmax[s->fpcr_ah][a->esz])
820
+TRANS_FEAT(FMAX_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmax[s->fpcr_ah][a->esz])
821
+TRANS_FEAT(BFMAX_n1, aa64_sme2_sve_b16b16, do_zzz_n1_fpst, a,
822
+ s->fpcr_ah ? gen_helper_gvec_ah_fmax_b16 : gen_helper_gvec_fmax_b16)
823
+TRANS_FEAT(BFMAX_nn, aa64_sme2_sve_b16b16, do_zzz_nn_fpst, a,
824
+ s->fpcr_ah ? gen_helper_gvec_ah_fmax_b16 : gen_helper_gvec_fmax_b16)
825
826
static gen_helper_gvec_3_ptr * const f_vector_fmin[2][4] = {
832
- { gen_helper_gvec_fmin_b16,
827
+ { NULL,
828
gen_helper_gvec_fmin_h,
829
gen_helper_gvec_fmin_s,
830
gen_helper_gvec_fmin_d },
836
- { gen_helper_gvec_ah_fmin_b16,
831
+ { NULL,
832
gen_helper_gvec_ah_fmin_h,
833
gen_helper_gvec_ah_fmin_s,
834
gen_helper_gvec_ah_fmin_d },
835
};
841
-TRANS_FEAT(FMIN_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmin[s->fpcr_ah])
842
-TRANS_FEAT(FMIN_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmin[s->fpcr_ah])
836
+TRANS_FEAT(FMIN_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmin[s->fpcr_ah][a->esz])
837
+TRANS_FEAT(FMIN_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmin[s->fpcr_ah][a->esz])
838
+TRANS_FEAT(BFMIN_n1, aa64_sme2_sve_b16b16, do_zzz_n1_fpst, a,
839
+ s->fpcr_ah ? gen_helper_gvec_ah_fmin_b16 : gen_helper_gvec_fmin_b16)
840
+TRANS_FEAT(BFMIN_nn, aa64_sme2_sve_b16b16, do_zzz_nn_fpst, a,
841
+ s->fpcr_ah ? gen_helper_gvec_ah_fmin_b16 : gen_helper_gvec_fmin_b16)
842
843
static gen_helper_gvec_3_ptr * const f_vector_fmaxnm[4] = {
845
- gen_helper_gvec_fmaxnum_b16,
844
+ NULL,
845
gen_helper_gvec_fmaxnum_h,
846
gen_helper_gvec_fmaxnum_s,
847
gen_helper_gvec_fmaxnum_d,
848
};
850
-TRANS_FEAT(FMAXNM_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmaxnm)
851
-TRANS_FEAT(FMAXNM_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmaxnm)
849
+TRANS_FEAT(FMAXNM_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fmaxnm[a->esz])
850
+TRANS_FEAT(FMAXNM_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fmaxnm[a->esz])
851
+TRANS_FEAT(BFMAXNM_n1, aa64_sme2_sve_b16b16, do_zzz_n1_fpst, a,
852
+ gen_helper_gvec_fmaxnum_b16)
853
+TRANS_FEAT(BFMAXNM_nn, aa64_sme2_sve_b16b16, do_zzz_nn_fpst, a,
854
+ gen_helper_gvec_fmaxnum_b16)
855
856
static gen_helper_gvec_3_ptr * const f_vector_fminnm[4] = {
854
- gen_helper_gvec_fminnum_b16,
857
+ NULL,
858
gen_helper_gvec_fminnum_h,
859
gen_helper_gvec_fminnum_s,
860
gen_helper_gvec_fminnum_d,
861
};
859
-TRANS_FEAT(FMINNM_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fminnm)
860
-TRANS_FEAT(FMINNM_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fminnm)
862
+TRANS_FEAT(FMINNM_n1, aa64_sme2, do_zzz_n1_fpst, a, f_vector_fminnm[a->esz])
863
+TRANS_FEAT(FMINNM_nn, aa64_sme2, do_zzz_nn_fpst, a, f_vector_fminnm[a->esz])
864
+TRANS_FEAT(BFMINNM_n1, aa64_sme2_sve_b16b16, do_zzz_n1_fpst, a,
865
+ gen_helper_gvec_fminnum_b16)
866
+TRANS_FEAT(BFMINNM_nn, aa64_sme2_sve_b16b16, do_zzz_nn_fpst, a,
867
+ gen_helper_gvec_fminnum_b16)
868
869
static gen_helper_gvec_3_ptr * const f_vector_famax[4] = {
870
NULL,
@@ -865,7 +872,7 @@ static gen_helper_gvec_3_ptr * const f_vector_famax[4] = {
872
gen_helper_gvec_famax_s,
873
gen_helper_gvec_famax_d,
874
};
868
-TRANS_FEAT(FAMAX_nn, aa64_sme2_faminmax, do_zzz_nn_fpst, a, f_vector_famax)
875
+TRANS_FEAT(FAMAX_nn, aa64_sme2_faminmax, do_zzz_nn_fpst, a, f_vector_famax[a->esz])
876
877
static gen_helper_gvec_3_ptr * const f_vector_famin[4] = {
878
NULL,
@@ -873,7 +880,7 @@ static gen_helper_gvec_3_ptr * const f_vector_famin[4] = {
880
gen_helper_gvec_famin_s,
881
gen_helper_gvec_famin_d,
882
};
876
-TRANS_FEAT(FAMIN_nn, aa64_sme2_faminmax, do_zzz_nn_fpst, a, f_vector_famin)
883
+TRANS_FEAT(FAMIN_nn, aa64_sme2_faminmax, do_zzz_nn_fpst, a, f_vector_famin[a->esz])
884
885
static gen_helper_gvec_3_ptr * const f_vector_fscale[4] = {
886
NULL,
@@ -881,8 +888,8 @@ static gen_helper_gvec_3_ptr * const f_vector_fscale[4] = {
888
gen_helper_gvec_fscale_s,
889
gen_helper_gvec_fscale_d,
890
};
884
-TRANS_FEAT(FSCALE_n1, aa64_sme2_f8cvt, do_zzz_n1_fpst, a, f_vector_fscale)
885
-TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_zzz_nn_fpst, a, f_vector_fscale)
891
+TRANS_FEAT(FSCALE_n1, aa64_sme2_f8cvt, do_zzz_n1_fpst, a, f_vector_fscale[a->esz])
892
+TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_zzz_nn_fpst, a, f_vector_fscale[a->esz])
893
894
/* Add/Sub vector Z[m] to each Z[n*N] with result in ZA[d*N]. */
895
static bool do_azz_n1(DisasContext *s, arg_azz_n *a, int esz,