target/hexagon: add GVec overrides for HVX saturating add/sub
Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260807152241.1576334-3-brian.cain@oss.qualcomm.com Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Aug 7, 2026 at 08:22 UTC
8c53023a26ec397fadaf3fd10404df1be57d2816
1 file changed
+87
target/hexagon/gen_tcg_hvx.h
+87
@@ -234,6 +234,93 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
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tcg_gen_gvec_sub(MO_32, VddV_off, VuuV_off, VvvV_off, \
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sizeof(MMVector) * 2, sizeof(MMVector) * 2)
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+#define fGEN_TCG_V6_vaddbsat(SHORTCODE) \
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+ tcg_gen_gvec_ssadd(MO_8, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vaddhsat(SHORTCODE) \
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+ tcg_gen_gvec_ssadd(MO_16, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vaddwsat(SHORTCODE) \
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+ tcg_gen_gvec_ssadd(MO_32, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vaddubsat(SHORTCODE) \
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+ tcg_gen_gvec_usadd(MO_8, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vadduhsat(SHORTCODE) \
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+ tcg_gen_gvec_usadd(MO_16, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vadduwsat(SHORTCODE) \
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+ tcg_gen_gvec_usadd(MO_32, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_PAIR_ADDSUB(OP, VECE, DST, SRC_A, SRC_B) \
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+ tcg_gen_gvec_##OP(VECE, DST, SRC_A, SRC_B, \
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+ 2 * VECTOR_SIZE_BYTE, 2 * VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vaddbsat_dv(SHORTCODE) \
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+ fGEN_TCG_PAIR_ADDSUB(ssadd, MO_8, VddV_off, VuuV_off, VvvV_off)
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+
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+#define fGEN_TCG_V6_vaddhsat_dv(SHORTCODE) \
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+ fGEN_TCG_PAIR_ADDSUB(ssadd, MO_16, VddV_off, VuuV_off, VvvV_off)
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+
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+#define fGEN_TCG_V6_vaddwsat_dv(SHORTCODE) \
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+ fGEN_TCG_PAIR_ADDSUB(ssadd, MO_32, VddV_off, VuuV_off, VvvV_off)
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+
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+#define fGEN_TCG_V6_vaddubsat_dv(SHORTCODE) \
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+ fGEN_TCG_PAIR_ADDSUB(usadd, MO_8, VddV_off, VuuV_off, VvvV_off)
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+
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+#define fGEN_TCG_V6_vadduhsat_dv(SHORTCODE) \
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+ fGEN_TCG_PAIR_ADDSUB(usadd, MO_16, VddV_off, VuuV_off, VvvV_off)
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+
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+#define fGEN_TCG_V6_vadduwsat_dv(SHORTCODE) \
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+ fGEN_TCG_PAIR_ADDSUB(usadd, MO_32, VddV_off, VuuV_off, VvvV_off)
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+
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+#define fGEN_TCG_V6_vsubbsat(SHORTCODE) \
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+ tcg_gen_gvec_sssub(MO_8, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vsubhsat(SHORTCODE) \
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+ tcg_gen_gvec_sssub(MO_16, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vsubwsat(SHORTCODE) \
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+ tcg_gen_gvec_sssub(MO_32, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vsububsat(SHORTCODE) \
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+ tcg_gen_gvec_ussub(MO_8, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vsubuhsat(SHORTCODE) \
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+ tcg_gen_gvec_ussub(MO_16, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vsubuwsat(SHORTCODE) \
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+ tcg_gen_gvec_ussub(MO_32, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vsubbsat_dv(SHORTCODE) \
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+ fGEN_TCG_PAIR_ADDSUB(sssub, MO_8, VddV_off, VuuV_off, VvvV_off)
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+
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+#define fGEN_TCG_V6_vsubhsat_dv(SHORTCODE) \
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+ fGEN_TCG_PAIR_ADDSUB(sssub, MO_16, VddV_off, VuuV_off, VvvV_off)
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+
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+#define fGEN_TCG_V6_vsubwsat_dv(SHORTCODE) \
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+ fGEN_TCG_PAIR_ADDSUB(sssub, MO_32, VddV_off, VuuV_off, VvvV_off)
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+
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+#define fGEN_TCG_V6_vsububsat_dv(SHORTCODE) \
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+ fGEN_TCG_PAIR_ADDSUB(ussub, MO_8, VddV_off, VuuV_off, VvvV_off)
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+
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+#define fGEN_TCG_V6_vsubuhsat_dv(SHORTCODE) \
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+ fGEN_TCG_PAIR_ADDSUB(ussub, MO_16, VddV_off, VuuV_off, VvvV_off)
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+
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+#define fGEN_TCG_V6_vsubuwsat_dv(SHORTCODE) \
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+ fGEN_TCG_PAIR_ADDSUB(ussub, MO_32, VddV_off, VuuV_off, VvvV_off)
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/* Vector shift right - various forms */
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#define fGEN_TCG_V6_vasrh(SHORTCODE) \
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do { \