hw/sd: Add Axiado SD host controller with eMMC PHY
This patch add a new model for Axiado SD host controller which is compatible with SDHCI 3.0 spec This device model also includes a eMMC PHY which helps to control SD/eMMC Signed-off-by: Kuan-Jui Chiu <kchiu@axiado.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260713073033.3883619-5-kchiu@axiado.com [PMM: Use HWADDR_PRIx] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Kuan-Jui Chiu committed
Aug 11, 2026 at 20:14 UTC
8c55a630c5b91fd7292fb11ee0e69a5914b66487
5 files changed
+147
MAINTAINERS
+2
@@ -1305,7 +1305,9 @@ M: Kuan-Jui Chiu <kchiu@axiado.com>
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L: qemu-arm@nongnu.org
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S: Maintained
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F: hw/arm/ax3000*.c
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+F: hw/*/axiado*.c
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F: include/hw/arm/ax3000*.h
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+F: include/hw/*/axiado*.h
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AVR Machines
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-------------
hw/sd/Kconfig
+4
@@ -23,3 +23,7 @@ config SDHCI_PCI
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config CADENCE_SDHCI
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bool
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select SDHCI
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+
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+config AXIADO_SDHCI
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+ bool
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+ select SDHCI
hw/sd/axiado_sdhci.c
new
+119
@@ -0,0 +1,119 @@
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+/*
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+ * Axiado SD Host Controller with embedded PHY
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+ *
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+ * Author: Kuan-Jui Chiu <kchiu@axiado.com>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "hw/sd/axiado_sdhci.h"
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+#include "sdhci-internal.h"
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+#include "qapi/error.h"
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+#include "hw/core/qdev-properties.h"
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+#include "qemu/log.h"
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+
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+#define EMMC_PHY_ID 0x00
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+#define EMMC_PHY_STATUS 0x50
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+
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+#define DLL_RDY (1u << 0)
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+#define CAL_DONE (1u << 6)
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+
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+static uint64_t emmc_phy_read(void *opaque, hwaddr offset, unsigned size)
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+{
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+ uint32_t val = 0x00;
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+
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+ switch (offset) {
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+ case EMMC_PHY_ID:
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+ val = 0x3dff6870;
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+ break;
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+ case EMMC_PHY_STATUS:
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+ val = DLL_RDY | CAL_DONE;
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+ break;
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+ default:
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+ qemu_log_mask(LOG_UNIMP,
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+ "Register 0x%" HWADDR_PRIx " not implemented\n", offset);
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+ break;
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+ }
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+
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+ return val;
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+}
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+
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+static void emmc_phy_write(void *opaque, hwaddr offset, uint64_t value,
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+ unsigned size)
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+{
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+ qemu_log_mask(LOG_UNIMP,
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+ "Register 0x%" HWADDR_PRIx " not implemented\n", offset);
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+}
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+
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+static const MemoryRegionOps emmc_phy_ops = {
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+ .read = emmc_phy_read,
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+ .write = emmc_phy_write,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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+ .impl = {
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+ .min_access_size = 4,
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+ .max_access_size = 4,
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+ },
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+ .valid = {
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+ .min_access_size = 4,
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+ .max_access_size = 4,
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+ }
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+};
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+
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+static void axiado_sdhci_realize(DeviceState *dev, Error **errp)
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+{
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+ AxiadoSDHCIState *s = AXIADO_SDHCI(dev);
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+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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+ SysBusDevice *sdhci_sbd;
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+
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+ qdev_prop_set_uint64(DEVICE(&s->sdhci), "capareg", 0x216737eed0b0);
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+ qdev_prop_set_uint64(DEVICE(&s->sdhci), "sd-spec-version", 3);
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+
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+ sdhci_sbd = SYS_BUS_DEVICE(&s->sdhci);
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+ if (!sysbus_realize(sdhci_sbd, errp)) {
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+ return;
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+ }
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+
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+ sysbus_init_mmio(sbd, sysbus_mmio_get_region(sdhci_sbd, 0));
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+
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+ /* Propagate IRQ from SDHCI and SD bus */
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+ sysbus_pass_irq(sbd, sdhci_sbd);
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+ s->sd_bus = qdev_get_child_bus(DEVICE(sdhci_sbd), "sd-bus");
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+
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+ /* Initialize eMMC PHY MMIO */
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+ memory_region_init_io(&s->emmc_phy, OBJECT(s), &emmc_phy_ops, s,
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+ "axiado.emmc-phy", 0x1000);
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+
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+ sysbus_init_mmio(sbd, &s->emmc_phy);
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+}
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+
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+static void axiado_sdhci_instance_init(Object *obj)
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+{
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+ AxiadoSDHCIState *s = AXIADO_SDHCI(obj);
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+
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+ object_initialize_child(OBJECT(s), "sdhci", &s->sdhci,
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+ TYPE_SYSBUS_SDHCI);
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+}
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+
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+static void axiado_sdhci_class_init(ObjectClass *klass, const void *data)
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+{
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+ DeviceClass *dc = DEVICE_CLASS(klass);
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+
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+ dc->realize = axiado_sdhci_realize;
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+ dc->desc = "Axiado SD Host Controller with eMMC PHY";
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+}
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+
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+static const TypeInfo axiado_sdhci_info = {
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+ .name = TYPE_AXIADO_SDHCI,
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+ .parent = TYPE_SYS_BUS_DEVICE,
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+ .instance_size = sizeof(AxiadoSDHCIState),
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+ .instance_init = axiado_sdhci_instance_init,
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+ .class_init = axiado_sdhci_class_init,
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+};
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+
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+static void axiado_sdhci_register_types(void)
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+{
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+ type_register_static(&axiado_sdhci_info);
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+}
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+
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+type_init(axiado_sdhci_register_types);
hw/sd/meson.build
+1
@@ -10,3 +10,4 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sdhci.c'))
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system_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdhost.c'))
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system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_sdhci.c'))
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system_ss.add(when: 'CONFIG_CADENCE_SDHCI', if_true: files('cadence_sdhci.c'))
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+system_ss.add(when: 'CONFIG_AXIADO_SDHCI', if_true: files('axiado_sdhci.c'))
include/hw/sd/axiado_sdhci.h
new
+21
@@ -0,0 +1,21 @@
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+/*
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+ * Axiado SD Host Controller
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+ *
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+ * Author: Kuan-Jui Chiu <kchiu@axiado.com>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "hw/sd/sdhci.h"
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+#include "qom/object.h"
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+
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+#define TYPE_AXIADO_SDHCI "axiado-sdhci"
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+OBJECT_DECLARE_SIMPLE_TYPE(AxiadoSDHCIState, AXIADO_SDHCI)
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+
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+typedef struct AxiadoSDHCIState {
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+ SysBusDevice parent;
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+
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+ SDHCIState sdhci;
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+ MemoryRegion emmc_phy;
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+ BusState *sd_bus;
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+} AxiadoSDHCIState;