target/arm: GICv5 cpuif: Tag ICC_PPI_PRIORITYR<n> regs as ARM_CP_NO_RAW
The GICv5 system registers are all tagged with ARM_CP_NO_RAW, because we don't want them to use the standard mechanisms for migration or KVM state synchronization. (GICv5 handling of both migration and KVM support is a "will be implemented later" feature.) We missed this tag on the ICC_PPI_PRIORITYR<n>_EL1 registers; add it. Fixes: ef540c1d301 ("target/arm: GICv5 cpuif: Implement PPI priority registers") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Message-id: 20260615105029.2898872-4-peter.maydell@linaro.org
Peter Maydell committed
Jun 15, 2026 at 11:50 UTC
8c63fe8c157f40d94cf4a4373a2e02a5c77c26f6
1 file changed
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-1
target/arm/tcg/gicv5-cpuif.c
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@@ -950,7 +950,7 @@ void define_gicv5_cpuif_regs(ARMCPU *cpu)
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.name = name, .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 12,
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.crm = 14 + (i >> 3), .opc2 = i & 7,
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- .access = PL1_RW, .type = ARM_CP_IO,
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+ .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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.fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_priority[i]),
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.writefn = gic_ppi_priority_write, .raw_writefn = raw_write,
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};