@samitouri / QOSamiQemu / commits / 8c6cf9ef47

hw/arm/aspeed: Consolidate secure SRAM into SRAM array

Some Aspeed SoCs contain multiple SRAM regions with different sizes and MMIO mappings, such as internal SRAM and secure SRAM. The current implementation models secure SRAM separately from the generic SRAM representation, which complicates future multi-SRAM support and expansion. Increase ASPEED_SRAM_NUM to 2 and migrate secure SRAM to use the common SRAM array representation. Rename the secure SRAM memmap entry to ASPEED_DEV_SRAM1 and update AST10x0 to initialize both SRAM regions through sram[] and sram_size[]. This unifies SRAM-like regions under a common representation and prepares for future SoCs with additional SRAM regions. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>

Jamin Lin committed May 25, 2026 at 05:30 UTC 8c6cf9ef471e34f74fb1a1dc50d6916897994245
2 files changed +11 -11
hw/arm/aspeed_ast10x0.c
+9 -7
@@ -21,7 +21,7 @@
21
22 static const hwaddr aspeed_soc_ast1030_memmap[] = {
23 [ASPEED_DEV_SRAM0] = 0x00000000,
24 - [ASPEED_DEV_SECSRAM] = 0x79000000,
24 + [ASPEED_DEV_SRAM1] = 0x79000000, /* SEC SRAM */
25 [ASPEED_DEV_IOMEM] = 0x7E600000,
26 [ASPEED_DEV_PWM] = 0x7E610000,
27 [ASPEED_DEV_FMC] = 0x7E620000,
@@ -249,14 +249,16 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
249 memory_region_add_subregion(s->memory,
250 sc->memmap[ASPEED_DEV_SRAM0],
251 &s->sram[0]);
252 - memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
253 - sc->secsram_size, &err);
252 +
253 + /* Internal SEC SRAM */
254 + memory_region_init_ram(&s->sram[1], OBJECT(s), "sec.sram",
255 + sc->sram_size[1], &err);
256 if (err != NULL) {
257 error_propagate(errp, err);
258 return false;
259 }
258 - memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM],
259 - &s->secsram);
260 + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM1],
261 + &s->sram[1]);
262
263 /* SCU */
264 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
@@ -494,7 +496,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *data)
496 sc->valid_cpu_types = valid_cpu_types;
497 sc->silicon_rev = AST1030_A1_SILICON_REV;
498 sc->sram_size[0] = 0xc0000;
497 - sc->secsram_size = 0x40000; /* 256 * KiB */
499 + sc->sram_size[1] = 0x40000; /* SEC SRAM 256 * KiB */
500 sc->spis_num = 2;
501 sc->ehcis_num = 0;
502 sc->wdts_num = 4;
@@ -522,7 +524,7 @@ static void aspeed_soc_ast1060_class_init(ObjectClass *klass, const void *data)
524 sc->valid_cpu_types = valid_cpu_types;
525 sc->silicon_rev = AST1060_A2_SILICON_REV;
526 sc->sram_size[0] = 0xc0000;
525 - sc->secsram_size = 0x40000; /* 256 * KiB */
527 + sc->sram_size[1] = 0x40000; /* SEC SRAM 256 * KiB */
528 sc->spis_num = 2;
529 sc->wdts_num = 4;
530 sc->uarts_num = 1;
include/hw/arm/aspeed_soc.h
+2 -4
@@ -60,7 +60,7 @@
60 #define ASPEED_PCIE_NUM 3
61 #define ASPEED_INTC_NUM 2
62 #define ASPEED_IOEXP_NUM 2
63 -#define ASPEED_SRAM_NUM 1
63 +#define ASPEED_SRAM_NUM 2
64
65 struct AspeedSoCState {
66 DeviceState parent;
@@ -89,7 +89,6 @@ struct AspeedSoCState {
89 AspeedSBCState sbc;
90 AspeedSLIState sli;
91 AspeedSLIState sliio;
92 - MemoryRegion secsram;
92 UnimplementedDeviceState sbc_unimplemented;
93 AspeedSDMCState sdmc;
94 AspeedPWMState pwm;
@@ -173,7 +172,6 @@ struct AspeedSoCClass {
172 const char * const *valid_cpu_types;
173 uint32_t silicon_rev;
174 uint64_t sram_size[ASPEED_SRAM_NUM];
176 - uint64_t secsram_size;
175 int pcie_num;
176 int spis_num;
177 int sgpio_num;
@@ -225,10 +223,10 @@ enum {
223 ASPEED_DEV_SCU,
224 ASPEED_DEV_ADC,
225 ASPEED_DEV_SBC,
228 - ASPEED_DEV_SECSRAM,
226 ASPEED_DEV_EMMC_BC,
227 ASPEED_DEV_VIDEO,
228 ASPEED_DEV_SRAM0,
229 + ASPEED_DEV_SRAM1,
230 ASPEED_DEV_SDHCI,
231 ASPEED_DEV_GPIO,
232 ASPEED_DEV_GPIO_1_8V,