@samitouri / QOSamiQemu / commits / 8ce9e7af05

hw/misc/aspeed_scu: Add AST2700 SCUIO RNG control and data registers

Implement basic behavior for RNG_CTRL and RNG_DATA: - RNG_CTRL allows guest to enable/disable the RNG via the DIS bit. Only bits [0:3] and bit 5 are writable; other bits are masked. - The VLD bit (bit 31) is updated by the model to reflect the RNG enable state, and is not writable by the guest. - When RNG is enabled, reads from RNG_DATA return a newly generated random value. - When RNG is disabled, RNG_DATA return 0. This provides a minimal functional model of the RNG sufficient for software that expects readable random data without modeling full hardware behavior. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260706052701.1141740-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>

Jamin Lin committed Jul 6, 2026 at 05:27 UTC 8ce9e7af057f9f4763d3f8e7d2a3add791c7b084

1 file changed +25

hw/misc/aspeed_scu.c

+25

@@ -160,6 +160,11 @@

160 #define AST2700_SCU_CPU_SCRATCH_1 TO_REG(0x784)

161 #define AST2700_SCU_VGA_SCRATCH_0 TO_REG(0x900)

162

163 +#define AST2700_SCUIO_RNG_CTRL TO_REG(0xF0)

164 +#define AST2700_SCUIO_RNG_CTRL_MASK 0x2F

165 +#define AST2700_SCUIO_RNG_CTRL_DIS BIT(0)

166 +#define AST2700_SCUIO_RNG_CTRL_VLD BIT(31)

167 +#define AST2700_SCUIO_RNG_DATA TO_REG(0xF4)

168 #define AST2700_SCUIO_CLK_STOP_CTL_1 TO_REG(0x240)

169 #define AST2700_SCUIO_CLK_STOP_CLR_1 TO_REG(0x244)

170 #define AST2700_SCUIO_CLK_STOP_CTL_2 TO_REG(0x260)

@@ -954,6 +959,14 @@ static uint64_t aspeed_ast2700_scuio_read(void *opaque, hwaddr offset,

959 return 0;

960 }

961

962 + switch (reg) {

963 + case AST2700_SCUIO_RNG_DATA:

964 + if (!(s->regs[AST2700_SCUIO_RNG_CTRL] & AST2700_SCUIO_RNG_CTRL_DIS)) {

965 + s->regs[AST2700_SCUIO_RNG_DATA] = aspeed_scu_get_random();

966 + }

967 + break;

968 + }

969 +

970 trace_aspeed_ast2700_scuio_read(offset, size, s->regs[reg]);

971 return s->regs[reg];

972 }

@@ -977,6 +990,18 @@ static void aspeed_ast2700_scuio_write(void *opaque, hwaddr offset,

990 trace_aspeed_ast2700_scuio_write(offset, size, data);

991

992 switch (reg) {

993 + case AST2700_SCUIO_RNG_CTRL:

994 + data &= AST2700_SCUIO_RNG_CTRL_MASK;

995 + if (data & AST2700_SCUIO_RNG_CTRL_DIS) {

996 + data &= ~AST2700_SCUIO_RNG_CTRL_VLD;

997 + s->regs[AST2700_SCUIO_RNG_DATA] = 0;

998 + } else {

999 + s->regs[AST2700_SCUIO_RNG_DATA] = aspeed_scu_get_random();

1000 + data |= AST2700_SCUIO_RNG_CTRL_VLD;

1001 + }

1002 + s->regs[reg] = data;

1003 + updated = true;

1004 + break;

1005 case AST2700_SCUIO_CLK_STOP_CTL_1:

1006 case AST2700_SCUIO_CLK_STOP_CTL_2:

1007 s->regs[reg] |= data;