hw/core/machine: topology functions capabilities added
Add two functions one of which finds the lowest cache level defined in the cache description input, and the other checks if a given cache topology is defined at a particular cache level Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-id: 20260311160609.358-3-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alireza Sanaee committed
Apr 23, 2026 at 10:24 UTC
8d53896b44e210281e79cad34c8683744b8a433e
2 files changed
+57
hw/core/machine-smp.c
+52
@@ -406,3 +406,55 @@ bool machine_check_smp_cache(const MachineState *ms, Error **errp)
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return true;
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}
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+
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+/*
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+ * This function assumes L3 and L2 have unified cache and L1 is split L1d and
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+ * L1i.
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+ */
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+bool machine_find_lowest_level_cache_at_topo_level(const MachineState *ms,
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+ int *lowest_cache_level,
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+ CpuTopologyLevel topo_level)
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+{
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+ enum CacheLevelAndType cache_level;
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+ enum CpuTopologyLevel t;
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+
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+ for (cache_level = CACHE_LEVEL_AND_TYPE_L1D;
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+ cache_level < CACHE_LEVEL_AND_TYPE__MAX; cache_level++) {
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+ t = machine_get_cache_topo_level(ms, cache_level);
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+ if (t == topo_level) {
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+ /* Assume L1 is split into L1d and L1i caches. */
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+ if (cache_level == CACHE_LEVEL_AND_TYPE_L1D ||
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+ cache_level == CACHE_LEVEL_AND_TYPE_L1I) {
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+ *lowest_cache_level = 1; /* L1 */
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+ } else {
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+ /* Assume the other caches are unified. */
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+ *lowest_cache_level = cache_level;
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+ }
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+
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+ return true;
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+ }
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+ }
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+
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+ return false;
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+}
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+
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+/*
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+ * Check if there are caches defined at a particular level. It supports only
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+ * L1, L2 and L3 caches, but this can be extended to more levels as needed.
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+ *
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+ * Return True on success, False otherwise.
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+ */
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+bool machine_defines_cache_at_topo_level(const MachineState *ms,
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+ CpuTopologyLevel topology)
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+{
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+ enum CacheLevelAndType cache_level;
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+
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+ for (cache_level = CACHE_LEVEL_AND_TYPE_L1D;
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+ cache_level < CACHE_LEVEL_AND_TYPE__MAX; cache_level++) {
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+ if (machine_get_cache_topo_level(ms, cache_level) == topology) {
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+ return true;
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+ }
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+ }
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+
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+ return false;
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+}
include/hw/core/boards.h
+5
@@ -60,6 +60,11 @@ void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache,
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CpuTopologyLevel level);
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bool machine_check_smp_cache(const MachineState *ms, Error **errp);
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void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size);
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+bool machine_defines_cache_at_topo_level(const MachineState *ms,
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+ CpuTopologyLevel topology);
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+bool machine_find_lowest_level_cache_at_topo_level(const MachineState *ms,
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+ int *lowest_cache_level,
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+ CpuTopologyLevel topo_level);
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/**
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* machine_class_allow_dynamic_sysbus_dev: Add type to list of valid devices