target/loongarch: Use sys_state in cpu_helper.c when accessing CSR registers
When accessing CSR register in file cpu_helper.c, use sys_state rather than env. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@mailo.com> Tested-by: Song Gao <gaosong@loongson.cn> Message-ID: <20260605082552.175336-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
Bibo Mao committed
Jun 5, 2026 at 16:25 UTC
8d8cb6636634cf12bd9d46d4c7787b8e6ef6d2f3
1 file changed
+22
-19
target/loongarch/cpu_helper.c
+22
-19
@@ -20,27 +20,29 @@
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void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
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uint64_t *dir_width, unsigned int level)
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{
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+ CPUSysState *sys = env_sys(env);
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+
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switch (level) {
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case 1:
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- *dir_base = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_BASE);
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- *dir_width = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_WIDTH);
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+ *dir_base = FIELD_EX64(sys->CSR_PWCL, CSR_PWCL, DIR1_BASE);
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+ *dir_width = FIELD_EX64(sys->CSR_PWCL, CSR_PWCL, DIR1_WIDTH);
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break;
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case 2:
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- *dir_base = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR2_BASE);
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- *dir_width = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR2_WIDTH);
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+ *dir_base = FIELD_EX64(sys->CSR_PWCL, CSR_PWCL, DIR2_BASE);
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+ *dir_width = FIELD_EX64(sys->CSR_PWCL, CSR_PWCL, DIR2_WIDTH);
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break;
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case 3:
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- *dir_base = FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR3_BASE);
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- *dir_width = FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR3_WIDTH);
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+ *dir_base = FIELD_EX64(sys->CSR_PWCH, CSR_PWCH, DIR3_BASE);
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+ *dir_width = FIELD_EX64(sys->CSR_PWCH, CSR_PWCH, DIR3_WIDTH);
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break;
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case 4:
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- *dir_base = FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR4_BASE);
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- *dir_width = FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR4_WIDTH);
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+ *dir_base = FIELD_EX64(sys->CSR_PWCH, CSR_PWCH, DIR4_BASE);
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+ *dir_width = FIELD_EX64(sys->CSR_PWCH, CSR_PWCH, DIR4_WIDTH);
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break;
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default:
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/* level may be zero for ldpte */
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- *dir_base = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE);
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- *dir_width = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH);
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+ *dir_base = FIELD_EX64(sys->CSR_PWCL, CSR_PWCL, PTBASE);
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+ *dir_width = FIELD_EX64(sys->CSR_PWCL, CSR_PWCL, PTWIDTH);
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break;
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}
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}
@@ -156,13 +158,13 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
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vaddr address;
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TLBRet ret;
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MemTxResult ret1;
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-
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+ CPUSysState *sys = env_sys(env);
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address = context->addr;
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if ((address >> 63) & 0x1) {
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- base = env->CSR_PGDH;
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+ base = sys->CSR_PGDH;
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} else {
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- base = env->CSR_PGDL;
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+ base = sys->CSR_PGDL;
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}
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base &= palen_mask;
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@@ -315,8 +317,9 @@ TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
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int kernel_mode = mmu_idx == MMU_KERNEL_IDX;
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uint32_t plv, base_c, base_v;
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int64_t addr_high;
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- uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
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- uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
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+ CPUSysState *sys = env_sys(env);
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+ uint8_t da = FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, DA);
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+ uint8_t pg = FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, PG);
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vaddr address;
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/* Check PG and DA */
@@ -337,12 +340,12 @@ TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
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/* Check direct map window */
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for (int i = 0; i < 4; i++) {
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if (is_la64(env)) {
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- base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_64, VSEG);
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+ base_c = FIELD_EX64(sys->CSR_DMW[i], CSR_DMW_64, VSEG);
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} else {
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- base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_32, VSEG);
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+ base_c = FIELD_EX64(sys->CSR_DMW[i], CSR_DMW_32, VSEG);
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}
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- if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
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- context->physical = dmw_va2pa(env, address, env->CSR_DMW[i]);
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+ if ((plv & sys->CSR_DMW[i]) && (base_c == base_v)) {
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+ context->physical = dmw_va2pa(env, address, sys->CSR_DMW[i]);
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context->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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context->mmu_index = MMU_DA_IDX;
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return TLBRET_MATCH;