target/arm: Implement floating-point log and convert to integer (zeroing)
This is FLOGB, FCVTZS, FCVTZU. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260604234852.573178-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 4, 2026 at 16:48 UTC
8de1ba58af636d1844be43b9ea6e34ced302a057
2 files changed
+51
-2
target/arm/tcg/sve.decode
+16
@@ -1242,6 +1242,21 @@ FCVTZU_sd_m 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
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FCVTZS_dd_m 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
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FCVTZU_dd_m 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
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+FCVTZS_hh_z 01100100 01 011 11 0 110 ... ..... ..... @rd_pg_rn_e0
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+FCVTZU_hh_z 01100100 01 011 11 0 111 ... ..... ..... @rd_pg_rn_e0
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+FCVTZS_hs_z 01100100 01 011 11 1 100 ... ..... ..... @rd_pg_rn_e0
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+FCVTZU_hs_z 01100100 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
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+FCVTZS_hd_z 01100100 01 011 11 1 110 ... ..... ..... @rd_pg_rn_e0
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+FCVTZU_hd_z 01100100 01 011 11 1 111 ... ..... ..... @rd_pg_rn_e0
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+FCVTZS_ss_z 01100100 10 011 11 1 100 ... ..... ..... @rd_pg_rn_e0
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+FCVTZU_ss_z 01100100 10 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
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+FCVTZS_sd_z 01100100 11 011 11 1 100 ... ..... ..... @rd_pg_rn_e0
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+FCVTZU_sd_z 01100100 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
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+FCVTZS_ds_z 01100100 11 011 11 0 100 ... ..... ..... @rd_pg_rn_e0
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+FCVTZU_ds_z 01100100 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
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+FCVTZS_dd_z 01100100 11 011 11 1 110 ... ..... ..... @rd_pg_rn_e0
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+FCVTZU_dd_z 01100100 11 011 11 1 111 ... ..... ..... @rd_pg_rn_e0
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+
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# SVE floating-point round to integral value
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FRINTN_m 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn
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FRINTP_m 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn
@@ -1950,6 +1965,7 @@ FCVTLT_sd_z 01100100 11 0000 11 101 ... ..... ..... @rd_pg_rn_e0
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### SVE2 floating-point convert to integer
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FLOGB_m 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz
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+FLOGB_z 01100100 00 011 1101 esz:2 pg:3 rn:5 rd:5 &rpr_esz
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### SVE2 floating-point multiply-add long (vectors)
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FMLALB_zzzw 01100100 10 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
target/arm/tcg/translate-sve.c
+35
-2
@@ -4654,6 +4654,37 @@ TRANS_FEAT(FCVTZS_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
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TRANS_FEAT(FCVTZU_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
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gen_helper_sve_fcvtzu_dd, a, 0, FPST_A64)
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+TRANS_FEAT(FCVTZS_hh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzs_hh, a, 1, FPST_A64_F16)
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+TRANS_FEAT(FCVTZU_hh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzu_hh, a, 1, FPST_A64_F16)
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+TRANS_FEAT(FCVTZS_hs_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzs_hs, a, 1, FPST_A64_F16)
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+TRANS_FEAT(FCVTZU_hs_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzu_hs, a, 1, FPST_A64_F16)
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+TRANS_FEAT(FCVTZS_hd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzs_hd, a, 1, FPST_A64_F16)
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+TRANS_FEAT(FCVTZU_hd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzu_hd, a, 1, FPST_A64_F16)
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+
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+TRANS_FEAT(FCVTZS_ss_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzs_ss, a, 1, FPST_A64)
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+TRANS_FEAT(FCVTZU_ss_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzu_ss, a, 1, FPST_A64)
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+TRANS_FEAT(FCVTZS_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzs_sd, a, 1, FPST_A64)
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+TRANS_FEAT(FCVTZU_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzu_sd, a, 1, FPST_A64)
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+TRANS_FEAT(FCVTZS_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzs_ds, a, 1, FPST_A64)
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+TRANS_FEAT(FCVTZU_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzu_ds, a, 1, FPST_A64)
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+
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+TRANS_FEAT(FCVTZS_dd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzs_dd, a, 1, FPST_A64)
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+TRANS_FEAT(FCVTZU_dd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvtzu_dd, a, 1, FPST_A64)
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+
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static gen_helper_gvec_3_ptr * const frint_fns[] = {
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NULL,
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gen_helper_sve_frint_h,
@@ -8134,8 +8165,10 @@ static gen_helper_gvec_3_ptr * const flogb_fns[] = {
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NULL, gen_helper_flogb_h,
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gen_helper_flogb_s, gen_helper_flogb_d
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};
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-TRANS_FEAT(FLOGB_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz],
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- a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
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+TRANS_FEAT(FLOGB_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
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+ flogb_fns[a->esz], a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
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+TRANS_FEAT(FLOGB_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ flogb_fns[a->esz], a, 1, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
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static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)
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{