target/riscv: Pass address as uint64_t in cpu_set_exception_base()
The corresponding field CPUArchState::resetvec is uint64_t anyway, no need to use target_ulong. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-27-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:54 UTC
8e09cda351e9df5b24e263c586bbc96c5432d029
2 files changed
+2
-2
target/riscv/cpu.c
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@@ -76,7 +76,7 @@ bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname)
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#ifndef CONFIG_USER_ONLY
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/* This is used in runtime only. */
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-void cpu_set_exception_base(int vp_index, target_ulong address)
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+void cpu_set_exception_base(int vp_index, uint64_t address)
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{
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RISCVCPU *cpu;
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CPUState *cs = qemu_get_cpu(vp_index);
target/riscv/cpu.h
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@@ -681,7 +681,7 @@ uint8_t riscv_cpu_get_fflags(CPURISCVState *env);
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void riscv_cpu_set_fflags(CPURISCVState *env, uint8_t);
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#ifndef CONFIG_USER_ONLY
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-void cpu_set_exception_base(int vp_index, target_ulong address);
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+void cpu_set_exception_base(int vp_index, uint64_t address);
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#endif
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FIELD(TB_FLAGS, MEM_IDX, 0, 3)