hw/riscv/fdt_common.c: create create_fdt_socket_cpu_internal()
The sifive_u board does not share the same CPU socket FDT bits from the other boards. In particular the riscv,isa creation is done using either CPU0 from soc.e_cpus.harts, and for all other CPUs soc.u_cups.harts is used. It would be too cumbersome to add all these details in the common code so we're going to add a special sifive_u only helper that shares the common bits with the common helper used by the other boards. create_fdt_socket_cpu_internal() contains the common bits shared between the sifive_u board and the rest. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260615203734.954428-13-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
Jun 15, 2026 at 17:37 UTC
8e75c341869049cbeeac5ce9a1a8076c08bdcccc
1 file changed
+65
-43
hw/riscv/fdt-common.c
+65
-43
@@ -94,28 +94,29 @@ void fdt_create_cpu_socket_subnode(void *fdt, uint64_t timebase_frequency)
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qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
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}
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-void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts,
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- int socket_id, int num_harts_socket,
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- int socket_hartid_base, uint32_t *phandle,
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- uint32_t *intc_phandles, bool numa_enabled,
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- bool is_32_bit)
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+static void
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+create_fdt_socket_cpu_internal(void *fdt, char *clust_name, RISCVCPU *cpu_ptr,
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+ int cpu, int socket_id, int socket_hartid_base,
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+ uint32_t *phandle, uint32_t *intc_phandles,
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+ bool numa_enabled, bool is_32_bit)
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{
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- g_autofree char *clust_name = NULL;
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- uint32_t cpu_phandle;
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-
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- clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket_id);
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- qemu_fdt_add_subnode(fdt, clust_name);
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-
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- for (int cpu = num_harts_socket - 1; cpu >= 0; cpu--) {
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- RISCVCPU *cpu_ptr = &socket_harts[cpu];
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+ g_autofree char *cpu_name = NULL;
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+ g_autofree char *core_name = NULL;
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+ g_autofree char *intc_name = NULL;
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+ uint32_t cpu_phandle = (*phandle)++;
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+ bool is_sifive_u = cpu_ptr == NULL;
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+
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+ cpu_name = g_strdup_printf("/cpus/cpu@%d", socket_hartid_base + cpu);
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+
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+ /*
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+ * The sifive_u board has an exclusive satp and riscv,isa
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+ * schema that can't be shared with other boards, so part
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+ * of the CPU FDT creation (i.e. the /cpus/cpu@N subnode)
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+ * is still being done by the board.
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+ */
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+ if (!is_sifive_u) {
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int8_t satp_mode_max = cpu_ptr->cfg.max_satp_mode;
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- g_autofree char *cpu_name = NULL;
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- g_autofree char *core_name = NULL;
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- g_autofree char *intc_name = NULL;
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-
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- cpu_phandle = (*phandle)++;
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- cpu_name = g_strdup_printf("/cpus/cpu@%d", socket_hartid_base + cpu);
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qemu_fdt_add_subnode(fdt, cpu_name);
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if (satp_mode_max != -1) {
@@ -140,30 +141,51 @@ void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts,
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qemu_fdt_setprop_cell(fdt, cpu_name, "riscv,cbop-block-size",
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cpu_ptr->cfg.cbop_blocksize);
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}
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+ }
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- qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
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- qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
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- qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
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- socket_hartid_base + cpu);
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- qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
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- if (numa_enabled) {
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- qemu_fdt_setprop_cell(fdt, cpu_name, "numa-node-id", socket_id);
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- }
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- qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
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-
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- intc_phandles[cpu] = (*phandle)++;
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-
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- intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
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- qemu_fdt_add_subnode(fdt, intc_name);
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- qemu_fdt_setprop_cell(fdt, intc_name, "phandle",
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- intc_phandles[cpu]);
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- qemu_fdt_setprop_string(fdt, intc_name, "compatible",
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- "riscv,cpu-intc");
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- qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
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- qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
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-
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- core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
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- qemu_fdt_add_subnode(fdt, core_name);
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- qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
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+ qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
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+ qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
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+ qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
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+ socket_hartid_base + cpu);
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+ qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
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+ if (numa_enabled) {
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+ qemu_fdt_setprop_cell(fdt, cpu_name, "numa-node-id", socket_id);
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+ }
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+ qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
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+
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+ intc_phandles[cpu] = (*phandle)++;
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+
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+ intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
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+ qemu_fdt_add_subnode(fdt, intc_name);
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+ qemu_fdt_setprop_cell(fdt, intc_name, "phandle",
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+ intc_phandles[cpu]);
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+ qemu_fdt_setprop_string(fdt, intc_name, "compatible",
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+ "riscv,cpu-intc");
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+ qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
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+ qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
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+
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+ core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
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+ qemu_fdt_add_subnode(fdt, core_name);
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+ qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
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+}
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+
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+void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts,
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+ int socket_id, int num_harts_socket,
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+ int socket_hartid_base, uint32_t *phandle,
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+ uint32_t *intc_phandles, bool numa_enabled,
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+ bool is_32_bit)
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+{
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+ g_autofree char *clust_name = NULL;
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+
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+ clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket_id);
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+ qemu_fdt_add_subnode(fdt, clust_name);
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+
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+ for (int cpu = num_harts_socket - 1; cpu >= 0; cpu--) {
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+ RISCVCPU *cpu_ptr = &socket_harts[cpu];
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+
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+ create_fdt_socket_cpu_internal(fdt, clust_name, cpu_ptr, cpu,
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+ socket_id, socket_hartid_base,
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+ phandle, intc_phandles, numa_enabled,
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+ is_32_bit);
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}
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}