target/arm: Enable FEAT_SVE_AES2 for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260826174213.614571-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 26, 2026 at 10:42 UTC
90789a83fb8b608f08a2716a3517c5ad743b3823
3 files changed
+3
-1
docs/system/arm/emulation.rst
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@@ -199,6 +199,7 @@ the following architecture extensions:
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- FEAT_SSVE_FP8FMA (SVE2 FP8 multiply-accumulate to half-precision and single-precision instructions in Streaming SVE mode)
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- FEAT_SVE (Scalable Vector Extension)
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- FEAT_SVE_AES (Scalable Vector AES instructions)
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+- FEAT_SVE_AES2 (SVE multi-vector Advanced Encryption Standard and 128-bit polynomial multiply long instructions)
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- FEAT_SVE_B16B16 (Non-widening BFloat16 arithmetic for SVE2)
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- FEAT_SVE_BFSCALE (BFloat16 Floating-Point Adjust Exponent)
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- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions)
linux-user/aarch64/elfload.c
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@@ -182,6 +182,7 @@ abi_ulong get_elf_hwcap(CPUState *cs)
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GET_FEATURE_ID(aa64_sme2p2, ARM_HWCAP_A64_SME2P2);
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GET_FEATURE_ID(aa64_sve_bfscale, ARM_HWCAP_A64_SVE_BFSCALE);
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GET_FEATURE_ID(aa64_ssve_bitperm, ARM_HWCAP_A64_SME_SBITPERM);
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+ GET_FEATURE_ID(aa64_sve_aes2, ARM_HWCAP_A64_SVE_AES2);
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return hwcaps;
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}
target/arm/tcg/cpu64.c
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-1
@@ -1471,7 +1471,7 @@ void aarch64_max_v9_tcg_initfn(Object *obj)
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t = GET_IDREG(isar, ID_AA64ZFR0);
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t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 3); /* v9.4: FEAT_SVE2p2 */
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- t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMULL128 */
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+ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 3); /* v9.5: FEAT_SVE_AES2 */
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t = FIELD_DP64(t, ID_AA64ZFR0, ELTPERM, 1); /* v9.4: FEAT_SVE2p2 */
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t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitPerm */
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t = FIELD_DP64(t, ID_AA64ZFR0, B16B16, 2); /* v9.2: FEAT_SVE_BFSCALE */