@samitouri / QOSamiQemu / commits / 922c474cd9

target/ppc: Move GPR atomic load/store instructions to decodetree

Move below instructions to decodetree specification: lwat, stwat : X-form (word atomic, ISA 3.0) ldat, stdat : X-form (doubleword atomic, ISA 3.0) The legacy gen_ld_atomic()/gen_st_atomic() functions that read register fields and the function code from ctx->opcode are replaced by new do_ld_atomic()/do_st_atomic() helpers in fixedpoint-impl.c.inc that use the pre-extracted decodetree argument fields (a->rt, a->ra, a->rb) directly. The RB field carries the Function Code (FC) selecting the atomic operation. gen_fetch_inc_conditional() is similarly moved and refactored to accept the destination register number as an explicit parameter instead of extracting it from ctx->opcode. Checked with '-d in_asm,op'. The printed TCG ops may differ from the pre-refactor log because EA now uses do_ea_calc(ctx, ra, 0), which lowers as GPR[ra] + 0 (then narrow in 32-bit mode) instead of mov/ext32u from ra alone. Signed-off-by: Aboorva Devarajan <aboorvad@linux.ibm.com> Reviewed-by: Nikhil Kumar Singh <nikhilks@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-13-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>

Aboorva Devarajan committed Aug 27, 2026 at 18:59 UTC 922c474cd976b036a3d266ff80f0a66a61349e27
3 files changed +221 -212
target/ppc/insn32.decode
+7
@@ -343,6 +343,13 @@ LSKU 111010 ..... ..... ............. 0 11 @DD
343 LCXU 111010 ..... ..... ............. 1 11 @DD
344
345
346 +### Fixed-Point Atomic Load/Store Instructions
347 +
348 +LWAT 011111 ..... ..... ..... 1001000110 - @X
349 +STWAT 011111 ..... ..... ..... 1011000110 - @X
350 +LDAT 011111 ..... ..... ..... 1001100110 - @X
351 +STDAT 011111 ..... ..... ..... 1011100110 - @X
352 +
353 ### Fixed-Point Store Instructions
354
355 STB 100110 ..... ..... ................ @D
target/ppc/translate.c
-212
@@ -2741,212 +2741,6 @@ static void gen_isync(DisasContext *ctx)
2741 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
2742 }
2743
2744 -static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
2745 - TCGv EA, TCGCond cond, int addend)
2746 -{
2747 - TCGv t = tcg_temp_new();
2748 - TCGv t2 = tcg_temp_new();
2749 - TCGv u = tcg_temp_new();
2750 -
2751 - tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
2752 - tcg_gen_addi_tl(t2, EA, memop_size(memop));
2753 - tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
2754 - tcg_gen_addi_tl(u, t, addend);
2755 -
2756 - /* E.g. for fetch and increment bounded... */
2757 - /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
2758 - tcg_gen_movcond_tl(cond, u, t, t2, u, t);
2759 - tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
2760 -
2761 - /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
2762 - tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t,
2763 - tcg_constant_tl(1 << (memop_size(memop) * 8 - 1)));
2764 -}
2765 -
2766 -static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
2767 -{
2768 - uint32_t gpr_FC = FC(ctx->opcode);
2769 - TCGv EA = tcg_temp_new();
2770 - int rt = rD(ctx->opcode);
2771 - bool need_serial;
2772 - TCGv src, dst;
2773 -
2774 - gen_addr_register(ctx, EA);
2775 - dst = cpu_gpr[rt];
2776 - src = cpu_gpr[(rt + 1) & 31];
2777 -
2778 - need_serial = false;
2779 - memop |= MO_ALIGN;
2780 - switch (gpr_FC) {
2781 - case 0: /* Fetch and add */
2782 - tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
2783 - break;
2784 - case 1: /* Fetch and xor */
2785 - tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
2786 - break;
2787 - case 2: /* Fetch and or */
2788 - tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
2789 - break;
2790 - case 3: /* Fetch and 'and' */
2791 - tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
2792 - break;
2793 - case 4: /* Fetch and max unsigned */
2794 - tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
2795 - break;
2796 - case 5: /* Fetch and max signed */
2797 - tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
2798 - break;
2799 - case 6: /* Fetch and min unsigned */
2800 - tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
2801 - break;
2802 - case 7: /* Fetch and min signed */
2803 - tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
2804 - break;
2805 - case 8: /* Swap */
2806 - tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
2807 - break;
2808 -
2809 - case 16: /* Compare and swap not equal */
2810 - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2811 - need_serial = true;
2812 - } else {
2813 - TCGv t0 = tcg_temp_new();
2814 - TCGv t1 = tcg_temp_new();
2815 -
2816 - tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
2817 - if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
2818 - tcg_gen_mov_tl(t1, src);
2819 - } else {
2820 - tcg_gen_ext32u_tl(t1, src);
2821 - }
2822 - tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
2823 - cpu_gpr[(rt + 2) & 31], t0);
2824 - tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
2825 - tcg_gen_mov_tl(dst, t0);
2826 - }
2827 - break;
2828 -
2829 - case 24: /* Fetch and increment bounded */
2830 - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2831 - need_serial = true;
2832 - } else {
2833 - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
2834 - }
2835 - break;
2836 - case 25: /* Fetch and increment equal */
2837 - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2838 - need_serial = true;
2839 - } else {
2840 - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
2841 - }
2842 - break;
2843 - case 28: /* Fetch and decrement bounded */
2844 - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2845 - need_serial = true;
2846 - } else {
2847 - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
2848 - }
2849 - break;
2850 -
2851 - default:
2852 - /* invoke data storage error handler */
2853 - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
2854 - }
2855 -
2856 - if (need_serial) {
2857 - /* Restart with exclusive lock. */
2858 - gen_helper_exit_atomic(tcg_env);
2859 - ctx->base.is_jmp = DISAS_NORETURN;
2860 - }
2861 -}
2862 -
2863 -static void gen_lwat(DisasContext *ctx)
2864 -{
2865 - gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
2866 -}
2867 -
2868 -#ifdef TARGET_PPC64
2869 -static void gen_ldat(DisasContext *ctx)
2870 -{
2871 - gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ));
2872 -}
2873 -#endif
2874 -
2875 -static void gen_st_atomic(DisasContext *ctx, MemOp memop)
2876 -{
2877 - uint32_t gpr_FC = FC(ctx->opcode);
2878 - TCGv EA = tcg_temp_new();
2879 - TCGv src, discard;
2880 -
2881 - gen_addr_register(ctx, EA);
2882 - src = cpu_gpr[rD(ctx->opcode)];
2883 - discard = tcg_temp_new();
2884 -
2885 - memop |= MO_ALIGN;
2886 - switch (gpr_FC) {
2887 - case 0: /* add and Store */
2888 - tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
2889 - break;
2890 - case 1: /* xor and Store */
2891 - tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
2892 - break;
2893 - case 2: /* Or and Store */
2894 - tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
2895 - break;
2896 - case 3: /* 'and' and Store */
2897 - tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
2898 - break;
2899 - case 4: /* Store max unsigned */
2900 - tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
2901 - break;
2902 - case 5: /* Store max signed */
2903 - tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
2904 - break;
2905 - case 6: /* Store min unsigned */
2906 - tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
2907 - break;
2908 - case 7: /* Store min signed */
2909 - tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
2910 - break;
2911 - case 24: /* Store twin */
2912 - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2913 - /* Restart with exclusive lock. */
2914 - gen_helper_exit_atomic(tcg_env);
2915 - ctx->base.is_jmp = DISAS_NORETURN;
2916 - } else {
2917 - TCGv t = tcg_temp_new();
2918 - TCGv t2 = tcg_temp_new();
2919 - TCGv s = tcg_temp_new();
2920 - TCGv s2 = tcg_temp_new();
2921 - TCGv ea_plus_s = tcg_temp_new();
2922 -
2923 - tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
2924 - tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop));
2925 - tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
2926 - tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
2927 - tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
2928 - tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
2929 - tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
2930 - }
2931 - break;
2932 - default:
2933 - /* invoke data storage error handler */
2934 - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
2935 - }
2936 -}
2937 -
2938 -static void gen_stwat(DisasContext *ctx)
2939 -{
2940 - gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
2941 -}
2942 -
2943 -#ifdef TARGET_PPC64
2944 -static void gen_stdat(DisasContext *ctx)
2945 -{
2946 - gen_st_atomic(ctx, DEF_MEMOP(MO_UQ));
2947 -}
2948 -#endif
2949 -
2744 /* wait */
2745 static void gen_wait(DisasContext *ctx)
2746 {
@@ -5571,12 +5365,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
5365 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
5366 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
5367 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
5574 -GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
5575 -GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
5576 -#if defined(TARGET_PPC64)
5577 -GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
5578 -GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
5579 -#endif
5368 /* ISA v3.0 changed the extended opcode from 62 to 30 */
5369 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT),
5370 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300),
target/ppc/translate/fixedpoint-impl.c.inc
+214
@@ -1646,3 +1646,217 @@ static bool trans_SRAWI(DisasContext *ctx, arg_SRAWI *a)
1646 }
1647 return true;
1648 }
1649 +
1650 +static void do_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
1651 + TCGv EA, int rt,
1652 + TCGCond cond, int addend)
1653 +{
1654 + TCGv t = tcg_temp_new();
1655 + TCGv t2 = tcg_temp_new();
1656 + TCGv u = tcg_temp_new();
1657 +
1658 + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
1659 + tcg_gen_addi_tl(t2, EA, memop_size(memop));
1660 + tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
1661 + tcg_gen_addi_tl(u, t, addend);
1662 +
1663 + /* mem(EA,s) = (t cond t2 ? u = t + addend : t) */
1664 + tcg_gen_movcond_tl(cond, u, t, t2, u, t);
1665 + tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
1666 +
1667 + /* RT = (t cond t2 ? t : 1<<(s*8-1)) */
1668 + tcg_gen_movcond_tl(cond, cpu_gpr[rt], t, t2, t,
1669 + tcg_constant_tl(1 << (memop_size(memop) * 8 - 1)));
1670 +}
1671 +
1672 +/*
1673 + * Fixed-Point Atomic Load/Store Instructions
1674 + *
1675 + * In the X-form encoding the RB field carries the Function Code (FC)
1676 + * that selects the atomic operation. EA is computed from RA alone.
1677 + */
1678 +static bool do_ld_atomic(DisasContext *ctx, arg_X *a, MemOp memop)
1679 +{
1680 + TCGv EA, dst, src;
1681 + bool need_serial;
1682 +
1683 + REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1684 +
1685 + EA = do_ea_calc(ctx, a->ra, tcg_constant_tl(0));
1686 + dst = cpu_gpr[a->rt];
1687 + src = cpu_gpr[(a->rt + 1) & 31];
1688 +
1689 + need_serial = false;
1690 + memop |= MO_ALIGN;
1691 + switch (a->rb) {
1692 + case 0: /* Fetch and add */
1693 + tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
1694 + break;
1695 + case 1: /* Fetch and xor */
1696 + tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
1697 + break;
1698 + case 2: /* Fetch and or */
1699 + tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
1700 + break;
1701 + case 3: /* Fetch and 'and' */
1702 + tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
1703 + break;
1704 + case 4: /* Fetch and max unsigned */
1705 + tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
1706 + break;
1707 + case 5: /* Fetch and max signed */
1708 + tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
1709 + break;
1710 + case 6: /* Fetch and min unsigned */
1711 + tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
1712 + break;
1713 + case 7: /* Fetch and min signed */
1714 + tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
1715 + break;
1716 + case 8: /* Swap */
1717 + tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
1718 + break;
1719 +
1720 + case 16: /* Compare and swap not equal */
1721 + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
1722 + need_serial = true;
1723 + } else {
1724 + TCGv t0 = tcg_temp_new();
1725 + TCGv t1 = tcg_temp_new();
1726 +
1727 + tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
1728 + if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
1729 + tcg_gen_mov_tl(t1, src);
1730 + } else {
1731 + tcg_gen_ext32u_tl(t1, src);
1732 + }
1733 + tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
1734 + cpu_gpr[(a->rt + 2) & 31], t0);
1735 + tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
1736 + tcg_gen_mov_tl(dst, t0);
1737 + }
1738 + break;
1739 +
1740 + case 24: /* Fetch and increment bounded */
1741 + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
1742 + need_serial = true;
1743 + } else {
1744 + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_NE, 1);
1745 + }
1746 + break;
1747 + case 25: /* Fetch and increment equal */
1748 + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
1749 + need_serial = true;
1750 + } else {
1751 + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_EQ, 1);
1752 + }
1753 + break;
1754 + case 28: /* Fetch and decrement bounded */
1755 + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
1756 + need_serial = true;
1757 + } else {
1758 + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_NE, -1);
1759 + }
1760 + break;
1761 +
1762 + default:
1763 + /* invoke data storage error handler */
1764 + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
1765 + }
1766 +
1767 + if (need_serial) {
1768 + /* Restart with exclusive lock. */
1769 + gen_helper_exit_atomic(tcg_env);
1770 + ctx->base.is_jmp = DISAS_NORETURN;
1771 + }
1772 + return true;
1773 +}
1774 +
1775 +static bool do_st_atomic(DisasContext *ctx, arg_X *a, MemOp memop)
1776 +{
1777 + TCGv EA, src, discard;
1778 +
1779 + REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1780 +
1781 + EA = do_ea_calc(ctx, a->ra, tcg_constant_tl(0));
1782 + src = cpu_gpr[a->rt];
1783 + discard = tcg_temp_new();
1784 +
1785 + memop |= MO_ALIGN;
1786 + switch (a->rb) {
1787 + case 0: /* add and Store */
1788 + tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
1789 + break;
1790 + case 1: /* xor and Store */
1791 + tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
1792 + break;
1793 + case 2: /* Or and Store */
1794 + tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
1795 + break;
1796 + case 3: /* 'and' and Store */
1797 + tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
1798 + break;
1799 + case 4: /* Store max unsigned */
1800 + tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
1801 + break;
1802 + case 5: /* Store max signed */
1803 + tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
1804 + break;
1805 + case 6: /* Store min unsigned */
1806 + tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
1807 + break;
1808 + case 7: /* Store min signed */
1809 + tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
1810 + break;
1811 + case 24: /* Store twin */
1812 + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
1813 + /* Restart with exclusive lock. */
1814 + gen_helper_exit_atomic(tcg_env);
1815 + ctx->base.is_jmp = DISAS_NORETURN;
1816 + } else {
1817 + TCGv t = tcg_temp_new();
1818 + TCGv t2 = tcg_temp_new();
1819 + TCGv s = tcg_temp_new();
1820 + TCGv s2 = tcg_temp_new();
1821 + TCGv ea_plus_s = tcg_temp_new();
1822 +
1823 + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
1824 + tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop));
1825 + tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
1826 + tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
1827 + tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
1828 + tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
1829 + tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
1830 + }
1831 + break;
1832 + default:
1833 + /* invoke data storage error handler */
1834 + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
1835 + }
1836 + return true;
1837 +}
1838 +
1839 +TRANS(LWAT, do_ld_atomic, DEF_MEMOP(MO_UL))
1840 +TRANS(STWAT, do_st_atomic, DEF_MEMOP(MO_UL))
1841 +
1842 +static bool trans_LDAT(DisasContext *ctx, arg_LDAT *a)
1843 +{
1844 + REQUIRE_64BIT(ctx);
1845 +#if defined(TARGET_PPC64)
1846 + return do_ld_atomic(ctx, a, DEF_MEMOP(MO_UQ));
1847 +#else
1848 + qemu_build_not_reached();
1849 +#endif
1850 + return true;
1851 +}
1852 +
1853 +static bool trans_STDAT(DisasContext *ctx, arg_STDAT *a)
1854 +{
1855 + REQUIRE_64BIT(ctx);
1856 +#if defined(TARGET_PPC64)
1857 + return do_st_atomic(ctx, a, DEF_MEMOP(MO_UQ));
1858 +#else
1859 + qemu_build_not_reached();
1860 +#endif
1861 + return true;
1862 +}