disas/riscv.c: add 'cbo' insns to disassembler
We forgot to add 'cbo' insns to disas/riscv.c. The result is that the disassembler recognizes all of them as 'lq', an insn that happens to share the same opcode space. While we're at it reorder cbo_* entries in insn32.decode using opcode order instead of insn name. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3480 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260519204714.1376551-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
May 19, 2026 at 17:47 UTC
9273cda72293ed2f414a0f239c4ac78fb7838c0e
2 files changed
+29
-2
disas/riscv.c
+28
-1
@@ -985,6 +985,10 @@ typedef enum {
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rv_op_ssamoswap_d = 953,
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rv_op_c_sspush = 954,
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rv_op_c_sspopchk = 955,
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+ rv_op_cbo_inval = 956,
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+ rv_op_cbo_clean = 957,
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+ rv_op_cbo_flush = 958,
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+ rv_op_cbo_zero = 959,
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} rv_op;
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/* register names */
@@ -2255,6 +2259,10 @@ const rv_opcode_data rvi_opcode_data[] = {
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rv_op_sspush, 0 },
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{ "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk,
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rv_op_sspopchk, 0 },
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+ { "cbo.inval", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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+ { "cbo.clean", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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+ { "cbo.flush", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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+ { "cbo.zero", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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};
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/* CSR names */
@@ -2876,7 +2884,26 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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switch ((inst >> 12) & 0b111) {
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case 0: op = rv_op_fence; break;
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case 1: op = rv_op_fence_i; break;
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- case 2: op = rv_op_lq; break;
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+ case 2:
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+ /*
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+ * 'lq' shares the "(...) 010 ..... 0001111" opcode space
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+ * with 'cbo' insns. Check the next 5 bits to select
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+ * what we want:
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+ *
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+ * cbo_inval 0000000 00000 ..... 010 00000 0001111
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+ * cbo_clean 0000000 00001 ..... 010 00000 0001111
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+ * cbo_flush 0000000 00010 ..... 010 00000 0001111
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+ * cbo_zero 0000000 00100 ..... 010 00000 0001111
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+ *
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+ * Anything that doesn't match these will default to 'lq'.
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+ */
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+ switch ((inst >> 17) & 0b11111) {
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+ case 0: op = rv_op_cbo_inval; break;
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+ case 1: op = rv_op_cbo_clean; break;
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+ case 2: op = rv_op_cbo_flush; break;
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+ case 4: op = rv_op_cbo_zero; break;
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+ default: op = rv_op_lq; break;
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+ }
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}
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break;
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case 4:
target/riscv/insn32.decode
+1
-1
@@ -207,9 +207,9 @@ ldu ............ ..... 111 ..... 0000011 @i
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{
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[
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# *** RV32 Zicbom Standard Extension ***
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+ cbo_inval 0000000 00000 ..... 010 00000 0001111 @sfence_vm
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cbo_clean 0000000 00001 ..... 010 00000 0001111 @sfence_vm
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cbo_flush 0000000 00010 ..... 010 00000 0001111 @sfence_vm
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- cbo_inval 0000000 00000 ..... 010 00000 0001111 @sfence_vm
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# *** RV32 Zicboz Standard Extension ***
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cbo_zero 0000000 00100 ..... 010 00000 0001111 @sfence_vm