target/arm: Move -cpu max stuff out of cpu32.c
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260827041557.775080-2-richard.henderson@linaro.org Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 26, 2026 at 21:15 UTC
92f6097af3648b036eaeabbbb81a263bbda1075a
3 files changed
+118
-111
target/arm/tcg/cpu-max-v8.c
new
+117
@@ -0,0 +1,117 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
2
+
3
+#include "qemu/osdep.h"
4
+#include "cpu.h"
5
+#include "internals.h"
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+
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+
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+/* Share AArch32 -cpu max features with AArch64. */
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+void aa32_max_features(ARMCPU *cpu)
10
+{
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+ uint32_t t;
12
+ ARMISARegisters *isar = &cpu->isar;
13
+
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+ /* Add additional features supported by QEMU */
15
+ t = GET_IDREG(isar, ID_ISAR5);
16
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
17
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
18
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
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+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
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+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
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+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
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+ SET_IDREG(isar, ID_ISAR5, t);
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+
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+ t = GET_IDREG(isar, ID_ISAR6);
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+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
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+ t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
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+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
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+ t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
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+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
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+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
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+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
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+ SET_IDREG(isar, ID_ISAR6, t);
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+
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+ t = cpu->isar.mvfr1;
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+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
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+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
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+ cpu->isar.mvfr1 = t;
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+
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+ t = cpu->isar.mvfr2;
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+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
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+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
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+ cpu->isar.mvfr2 = t;
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+
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+ FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
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+
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+ t = GET_IDREG(isar, ID_MMFR4);
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+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
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+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
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+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
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+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
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+ t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */
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+ SET_IDREG(isar, ID_MMFR4, t);
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+
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+ FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
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+
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+ t = GET_IDREG(isar, ID_PFR0);
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+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
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+ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
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+ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
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+ SET_IDREG(isar, ID_PFR0, t);
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+
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+ t = GET_IDREG(isar, ID_PFR2);
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+ t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
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+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
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+ SET_IDREG(isar, ID_PFR2, t);
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+
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+ t = GET_IDREG(isar, ID_DFR0);
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+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
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+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */
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+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
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+ SET_IDREG(isar, ID_DFR0, t);
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+
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+ /* Debug ID registers. */
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+
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+ /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
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+ t = 0x00008000;
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+ t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
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+ t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
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+ t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */
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+ t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
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+ t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
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+ t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
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+ cpu->isar.dbgdidr = t;
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+
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+ t = 0;
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+ t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
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+ t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
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+ t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
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+ t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
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+ t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
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+ t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
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+ t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
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+ t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
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+ cpu->isar.dbgdevid = t;
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+
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+ /* Bits[31:4] are RES0. */
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+ t = 0;
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+ t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
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+ cpu->isar.dbgdevid1 = t;
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+
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+ FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
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+}
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+
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+void aarch32_max_tcg_init(ARMCPU *cpu)
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+{
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+ aarch64_aa32_a57_init(cpu, false);
107
+ aa32_max_features(cpu);
108
+#ifdef CONFIG_USER_ONLY
109
+ /*
110
+ * Break with true ARMv8 and add back old-style VFP short-vector
111
+ * support. Only do this for user-mode, where -cpu max is the default,
112
+ * so that older v6 and v7 programs are more likely to work without
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+ * adjustment.
114
+ */
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+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
116
+#endif
117
+}
target/arm/tcg/cpu32.c
-111
@@ -758,114 +758,3 @@ static void arm_tcg_cpu_register_types(void)
758
type_init(arm_tcg_cpu_register_types)
759
760
#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
761
-
762
-/* Share AArch32 -cpu max features with AArch64. */
763
-void aa32_max_features(ARMCPU *cpu)
764
-{
765
- uint32_t t;
766
- ARMISARegisters *isar = &cpu->isar;
767
-
768
- /* Add additional features supported by QEMU */
769
- t = GET_IDREG(isar, ID_ISAR5);
770
- t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
771
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
772
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
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- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
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- t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
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- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
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- SET_IDREG(isar, ID_ISAR5, t);
777
-
778
- t = GET_IDREG(isar, ID_ISAR6);
779
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
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- t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
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- t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
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- t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
783
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
784
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
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- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
786
- SET_IDREG(isar, ID_ISAR6, t);
787
-
788
- t = cpu->isar.mvfr1;
789
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
790
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
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- cpu->isar.mvfr1 = t;
792
-
793
- t = cpu->isar.mvfr2;
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- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
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- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
796
- cpu->isar.mvfr2 = t;
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-
798
- FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
799
-
800
- t = GET_IDREG(isar, ID_MMFR4);
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- t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
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- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
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- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
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- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
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- t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */
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- SET_IDREG(isar, ID_MMFR4, t);
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-
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- FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
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-
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- t = GET_IDREG(isar, ID_PFR0);
811
- t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
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- t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
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- t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
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- SET_IDREG(isar, ID_PFR0, t);
815
-
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- t = GET_IDREG(isar, ID_PFR2);
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- t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
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- t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
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- SET_IDREG(isar, ID_PFR2, t);
820
-
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- t = GET_IDREG(isar, ID_DFR0);
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- t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
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- t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */
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- t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
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- SET_IDREG(isar, ID_DFR0, t);
826
-
827
- /* Debug ID registers. */
828
-
829
- /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
830
- t = 0x00008000;
831
- t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
832
- t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
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- t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */
834
- t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
835
- t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
836
- t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
837
- cpu->isar.dbgdidr = t;
838
-
839
- t = 0;
840
- t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
841
- t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
842
- t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
843
- t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
844
- t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
845
- t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
846
- t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
847
- t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
848
- cpu->isar.dbgdevid = t;
849
-
850
- /* Bits[31:4] are RES0. */
851
- t = 0;
852
- t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
853
- cpu->isar.dbgdevid1 = t;
854
-
855
- FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
856
-}
857
-
858
-void aarch32_max_tcg_init(ARMCPU *cpu)
859
-{
860
- aarch64_aa32_a57_init(cpu, false);
861
- aa32_max_features(cpu);
862
-#ifdef CONFIG_USER_ONLY
863
- /*
864
- * Break with true ARMv8 and add back old-style VFP short-vector
865
- * support. Only do this for user-mode, where -cpu max is the default,
866
- * so that older v6 and v7 programs are more likely to work without
867
- * adjustment.
868
- */
869
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
870
-#endif
871
-}
target/arm/tcg/meson.build
+1
@@ -65,6 +65,7 @@ arm_common_user_system_ss.add(
65
translate32_d,
66
vfp_d,
67
files(
68
+ 'cpu-max-v8.c',
69
'debug.c',
70
'gengvec.c',
71
'hflags.c',