target/hexagon: fix PC not advancing for non-COF TB-ending packets
Add hex_next_PC, a global mirroring CPUHexagonState::next_PC, and ctx->need_next_pc, so that gen_write_new_pc_addr() can write the branch target through hex_next_PC instead of hex_gpr[HEX_REG_PC] when a later unconditional write of PC is expected. gen_end_tb() then commits hex_next_PC into hex_gpr[HEX_REG_PC] at the end of the packet. Previously, non-COF instructions that still end a TB did not advance the PC, since next_PC's value was never written back into the PC register. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Jul 16, 2026 at 12:15 UTC
94a5b3ff4e371c8c04c6213e4383722bcafea2a8
3 files changed
+49
-19
target/hexagon/genptr.c
+11
-3
@@ -613,14 +613,22 @@ static void gen_write_new_pc_addr(DisasContext *ctx, TCGv addr,
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tcg_gen_brcondi_tl(cond, pred, 1, pred_false);
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}
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+ /*
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+ * If gen_end_tb() will unconditionally overwrite PC with hex_next_PC
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+ * (because this packet has a predicated COF that may not execute),
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+ * write the branch target there instead of directly into the PC
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+ * global, or the overwrite in gen_end_tb() would clobber it.
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+ */
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+ TCGv pc_wr = ctx->need_next_pc ? hex_next_PC : hex_gpr[HEX_REG_PC];
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+
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if (ctx->pkt.pkt_has_multi_cof) {
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/* If there are multiple branches in a packet, ignore the second one */
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- tcg_gen_movcond_tl(TCG_COND_NE, hex_gpr[HEX_REG_PC],
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+ tcg_gen_movcond_tl(TCG_COND_NE, pc_wr,
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ctx->branch_taken, tcg_constant_tl(0),
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- hex_gpr[HEX_REG_PC], addr);
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+ pc_wr, addr);
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tcg_gen_movi_tl(ctx->branch_taken, 1);
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} else {
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- tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], addr);
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+ tcg_gen_mov_tl(pc_wr, addr);
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}
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if (cond != TCG_COND_ALWAYS) {
target/hexagon/translate.c
+35
-16
@@ -54,6 +54,7 @@ static const AnalyzeInsn opcode_analyze[XX_LAST_OPCODE] = {
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TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
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TCGv hex_pred[NUM_PREGS];
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TCGv hex_slot_cancelled;
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+TCGv hex_next_PC;
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TCGv hex_new_value_usr;
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TCGv hex_store_addr[STORES_MAX];
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TCGv_i32 hex_store_width[STORES_MAX];
@@ -184,10 +185,16 @@ static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
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}
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}
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+static bool need_next_PC(DisasContext *ctx);
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+
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static void gen_end_tb(DisasContext *ctx)
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{
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gen_exec_counters(ctx);
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+ if (ctx->need_next_pc) {
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+ tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
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+ }
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+
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if (ctx->branch_cond != TCG_COND_NEVER) {
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if (ctx->branch_cond != TCG_COND_ALWAYS) {
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TCGLabel *skip = gen_new_label();
@@ -391,17 +398,25 @@ static bool pkt_ends_tb(Packet *pkt)
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static bool need_next_PC(DisasContext *ctx)
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{
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- /* Check for conditional control flow or HW loop end */
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- for (int i = 0; i < ctx->pkt.num_insns; i++) {
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- uint16_t opcode = ctx->pkt.insn[i].opcode;
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- if (GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) {
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- return true;
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- }
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- if (GET_ATTRIB(opcode, A_HWLOOP0_END) ||
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- GET_ATTRIB(opcode, A_HWLOOP1_END)) {
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- return true;
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+ Packet *pkt = &ctx->pkt;
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+ if (pkt->pkt_has_cof || ctx->pkt_ends_tb) {
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+ for (int i = 0; i < pkt->num_insns; i++) {
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+ uint16_t opcode = pkt->insn[i].opcode;
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+ if ((GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) ||
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+ GET_ATTRIB(opcode, A_HWLOOP0_END) ||
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+ GET_ATTRIB(opcode, A_HWLOOP1_END)) {
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+ return true;
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+ }
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}
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}
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+ /*
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+ * We end the TB on some instructions that do not change the flow (for
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+ * other reasons). In these cases, we must set pc too, as the insn won't
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+ * do it themselves.
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+ */
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+ if (ctx->pkt_ends_tb && !check_for_attrib(pkt, A_COF)) {
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+ return true;
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+ }
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return false;
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}
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@@ -637,12 +652,14 @@ static void gen_start_packet(DisasContext *ctx)
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ctx->branch_taken = NULL;
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if (ctx->pkt.pkt_has_cof) {
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ctx->branch_taken = tcg_temp_new();
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- if (ctx->pkt.pkt_has_multi_cof) {
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- tcg_gen_movi_tl(ctx->branch_taken, 0);
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- }
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- if (need_next_PC(ctx)) {
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- tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC);
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- }
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+ }
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+ if (ctx->pkt.pkt_has_multi_cof) {
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+ tcg_gen_movi_tl(ctx->branch_taken, 0);
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+ }
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+ ctx->pkt_ends_tb = pkt_ends_tb(&ctx->pkt);
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+ ctx->need_next_pc = need_next_PC(ctx);
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+ if (ctx->need_next_pc) {
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+ tcg_gen_movi_tl(hex_next_PC, next_PC);
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}
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/* Preload the predicated registers into get_result_gpr(ctx, i) */
@@ -1142,7 +1159,7 @@ static void gen_commit_packet(DisasContext *ctx)
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ctx->pkt.vhist_insn->generate(ctx);
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}
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1145
- if (pkt_ends_tb(&ctx->pkt) || ctx->base.is_jmp == DISAS_NORETURN) {
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+ if (ctx->pkt_ends_tb || ctx->base.is_jmp == DISAS_NORETURN) {
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gen_end_tb(ctx);
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}
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}
@@ -1327,6 +1344,8 @@ void hexagon_translate_init(void)
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}
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hex_new_value_usr = tcg_global_mem_new(tcg_env,
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offsetof(CPUHexagonState, new_value_usr), "new_value_usr");
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+ hex_next_PC = tcg_global_mem_new(tcg_env,
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+ offsetof(CPUHexagonState, next_PC), "next_PC");
1349
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for (i = 0; i < NUM_PREGS; i++) {
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hex_pred[i] = tcg_global_mem_new(tcg_env,
target/hexagon/translate.h
+3
@@ -40,6 +40,7 @@ typedef struct DisasContext {
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int reg_log_idx;
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DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
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DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS);
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+ bool pkt_ends_tb;
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bool implicit_usr_write;
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#ifndef CONFIG_USER_ONLY
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int greg_log[GREG_WRITES_MAX];
@@ -75,6 +76,7 @@ typedef struct DisasContext {
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DECLARE_BITMAP(insn_qregs_read, NUM_QREGS);
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bool pre_commit;
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bool need_commit;
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+ bool need_next_pc;
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TCGCond branch_cond;
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target_ulong branch_dest;
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bool is_tight_loop;
@@ -310,6 +312,7 @@ extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
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extern TCGv hex_pred[NUM_PREGS];
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extern TCGv hex_slot_cancelled;
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extern TCGv hex_new_value_usr;
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+extern TCGv hex_next_PC;
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extern TCGv hex_store_addr[STORES_MAX];
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extern TCGv_i32 hex_store_width[STORES_MAX];
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extern TCGv hex_store_val32[STORES_MAX];