target/arm: Update ID_AA64SMFR0_EL1 fields to ARM M.b
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
94b50236217ad856b575e13a2e1a5559cc5e71f5
1 file changed
+11
target/arm/cpu-features.h
+11
@@ -397,17 +397,28 @@ FIELD(ID_AA64ZFR0, F16MM, 48, 4)
397
FIELD(ID_AA64ZFR0, F32MM, 52, 4)
398
FIELD(ID_AA64ZFR0, F64MM, 56, 4)
399
400
+FIELD(ID_AA64SMFR0, SMOP4, 0, 1)
401
+FIELD(ID_AA64SMFR0, STMOP, 16, 1)
402
+FIELD(ID_AA64SMFR0, SFEXPA, 23, 1)
403
+FIELD(ID_AA64SMFR0, AES, 24, 1)
404
+FIELD(ID_AA64SMFR0, SBITPERM, 25, 1)
405
+FIELD(ID_AA64SMFR0, SF8DP2, 28, 1)
406
+FIELD(ID_AA64SMFR0, SF8DP4, 29, 1)
407
+FIELD(ID_AA64SMFR0, SF8FMA, 30, 1)
408
FIELD(ID_AA64SMFR0, F32F32, 32, 1)
409
FIELD(ID_AA64SMFR0, BI32I32, 33, 1)
410
FIELD(ID_AA64SMFR0, B16F32, 34, 1)
411
FIELD(ID_AA64SMFR0, F16F32, 35, 1)
412
FIELD(ID_AA64SMFR0, I8I32, 36, 4)
413
+FIELD(ID_AA64SMFR0, F8F32, 40, 1)
414
+FIELD(ID_AA64SMFR0, F8F16, 41, 1)
415
FIELD(ID_AA64SMFR0, F16F16, 42, 1)
416
FIELD(ID_AA64SMFR0, B16B16, 43, 1)
417
FIELD(ID_AA64SMFR0, I16I32, 44, 4)
418
FIELD(ID_AA64SMFR0, F64F64, 48, 1)
419
FIELD(ID_AA64SMFR0, I16I64, 52, 4)
420
FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
421
+FIELD(ID_AA64SMFR0, LUTv2, 60, 1)
422
FIELD(ID_AA64SMFR0, FA64, 63, 1)
423
424
FIELD(ID_AA64FPFR0, F8E5M2, 0, 1)