docs/system/arm/virt: Document accelerated SMMUv3 and Tegra241 CMDQV
Add subsections for accel=on (nested Stage-1/Stage-2 translation) and cmdqv (Tegra241 CMDQV hardware command queues) under "User-creatable SMMUv3 devices". Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Message-id: 20260623104003.36590-1-skolothumtho@nvidia.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Shameer Kolothum committed
Jun 23, 2026 at 11:40 UTC
94e3ad78004787b0dea9625544fb45d8cf037147
1 file changed
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docs/system/arm/virt.rst
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@@ -288,6 +288,32 @@ User-creatable SMMUv3 devices
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-device pxb-pcie,id=pcie.1,numa_node=1
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-device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1
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+ *Accelerated SMMUv3 (nested translation)*
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+
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+ The ``accel=on`` option enables hardware-accelerated nested translation
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+ for vfio-pci passthrough devices. In this mode the guest SMMU driver
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+ programs its own Stage-1 page tables, with the host SMMUv3 handling both
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+ Stage-1 (guest) and Stage-2 (host) translations in hardware. The host
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+ SMMUv3 must support nested translation. This mode requires the iommufd
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+ backend and is only supported when booting with ACPI (not device tree).
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+
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+ When ``accel=on``, QEMU automatically derives the values for the
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+ ``ril``, ``ats``, ``oas``, ``ssidsize`` and ``cmdqv`` sub-options
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+ from the host SMMUv3 capabilities unless they are set explicitly.
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+
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+ Example::
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+
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+ -device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.0,accel=on
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+
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+ *Accelerated SMMUv3 command queues (Tegra241 CMDQV)*
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+
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+ The ``cmdqv`` sub-option enables NVIDIA Tegra241 Command Queue
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+ Virtualization (CMDQV) on supported hosts. With CMDQV, each accelerated
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+ ``arm-smmuv3`` device gets dedicated hardware command queues and the
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+ guest issues SMMU invalidation commands directly to real hardware,
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+ bypassing QEMU and improving throughput for workloads that issue many
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+ invalidations. Without it, every invalidation command traps into QEMU.
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+
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Linux guest kernel configuration
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""""""""""""""""""""""""""""""""
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