target/arm: Implement FDOT (FP8 to FP32) for SVE
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-36-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
96a24f44622e6845a71c3480bfe7c23764adb05f
3 files changed
+44
target/arm/cpu-features.h
+5
@@ -1575,6 +1575,11 @@ static inline bool isar_feature_aa64_ssve_f8fma(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8FMA);
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}
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+static inline bool isar_feature_aa64_ssve_f8dp4(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8DP4);
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+}
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+
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static inline bool isar_feature_aa64_sme_b16b16(const ARMISARegisters *id)
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{
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, B16B16);
target/arm/tcg/sve.decode
+4
@@ -1874,6 +1874,8 @@ FMLALL_sb 01100100 00 1 rm:5 10 idxn:2 10 rn:5 rd:5 &rxx idxm=0
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FDOT_zzzz 01100100 00 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
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BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
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+FDOT_sb 01100100 01 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2
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+
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### SVE2 floating-point multiply-add long (indexed)
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FMLALB_zzxw 01100100 10 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2
@@ -1897,6 +1899,8 @@ FMLALL_idx_sb 01100100 idxn:2 1 .. rm:3 1100 .. rn:5 rd:5 \
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FDOT_zzxz 01100100 00 1 ..... 010000 ..... ..... @rrxr_2 esz=2
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BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2
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+FDOT_idx_sb 01100100 01 1 ..... 010001 ..... ..... @rrxr_2 esz=2
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+
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### SVE broadcast predicate element
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&psel esz pd pn pm rv imm
target/arm/tcg/translate-sve.c
+35
@@ -8391,3 +8391,38 @@ TRANS(FMLAL_idx_hb, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_hb)
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TRANS(FMLALL_sb, do_fmla_fp8, a, gen_helper_gvec_fmla_sb)
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TRANS(FMLALL_idx_sb, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_sb)
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+
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+static bool do_f8dp4(DisasContext *s, gen_helper_gvec_3_ptr *fn,
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+ int rd, int rn, int rm, int index)
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+{
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+ bool fp8dp4 = dc_isar_feature(aa64_f8dp4, s);
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+ bool ssve_fp8dp4 = dc_isar_feature(aa64_ssve_f8dp4, s);
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+ bool ok = false;
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+
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+ /* Feature detection and enabling are complex here. */
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+ if (!(ssve_fp8dp4 || (fp8dp4 && dc_isar_feature(aa64_sve2, s)))) {
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+ return false;
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+ }
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+ if (fpmr_access_check(s)) {
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+ if (fp8dp4) {
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+ s->is_nonstreaming = !ssve_fp8dp4;
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+ ok = sve_access_check(s);
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+ } else {
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+ ok = sme_sm_enabled_check(s);
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+ }
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+ }
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+
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+ if (ok) {
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+ unsigned vsz = vec_full_reg_size(s);
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+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
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+ vec_full_reg_offset(s, rn),
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+ vec_full_reg_offset(s, rm),
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+ tcg_env, vsz, vsz,
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+ index, fn);
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+ }
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+ return true;
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+}
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+
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+TRANS(FDOT_sb, do_f8dp4, gen_helper_gvec_fdot_sb, a->rd, a->rn, a->rm, 0)
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+TRANS(FDOT_idx_sb, do_f8dp4, gen_helper_gvec_fdot_idx_sb,
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+ a->rd, a->rn, a->rm, a->index)