target/arm/tcg/translate.c: replace TCGv with TCGv_va
We know this file is for 32-bit runtime target, so we can set TCG_ADDRESS_BITS. TCG_TYPE_VA is derived accordingly and is already passed to translator_loop. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260407222208.271838-16-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Pierrick Bouvier committed
Apr 23, 2026 at 10:24 UTC
96d18f3cc8dca6367666f002c1fae0f2dc2fd20e
1 file changed
+15
-14
target/arm/tcg/translate.c
+15
-14
@@ -22,7 +22,8 @@
22
23
#include "translate.h"
24
#include "translate-a32.h"
25
-#include "tcg/tcg-op.h"
25
+#define TCG_ADDRESS_BITS 32
26
+#include "tcg/tcg-op-mem.h"
27
#include "qemu/log.h"
28
#include "arm_ldst.h"
29
#include "semihosting/semihost.h"
@@ -910,14 +911,14 @@ MemOp pow2_align(unsigned i)
911
* that the address argument is TCGv_i32 rather than TCGv.
912
*/
913
913
-static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)
914
+static TCGv_va gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)
915
{
915
- TCGv addr = tcg_temp_new();
916
- tcg_gen_extu_i32_tl(addr, a32);
916
+ TCGv_va addr = tcgv_va_temp_new();
917
+ tcg_gen_mov_i32(addr, a32);
918
919
/* Not needed for user-mode BE32, where we use MO_BE instead. */
920
if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_32) {
920
- tcg_gen_xori_tl(addr, addr, 4 - (1 << (op & MO_SIZE)));
921
+ tcg_gen_xori_i32(addr, addr, 4 - (1 << (op & MO_SIZE)));
922
}
923
return addr;
924
}
@@ -929,21 +930,21 @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)
930
void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
931
TCGv_i32 a32, int index, MemOp opc)
932
{
932
- TCGv addr = gen_aa32_addr(s, a32, opc);
933
+ TCGv_va addr = gen_aa32_addr(s, a32, opc);
934
tcg_gen_qemu_ld_i32(val, addr, index, opc);
935
}
936
937
void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
938
TCGv_i32 a32, int index, MemOp opc)
939
{
939
- TCGv addr = gen_aa32_addr(s, a32, opc);
940
+ TCGv_va addr = gen_aa32_addr(s, a32, opc);
941
tcg_gen_qemu_st_i32(val, addr, index, opc);
942
}
943
944
void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
945
TCGv_i32 a32, int index, MemOp opc)
946
{
946
- TCGv addr = gen_aa32_addr(s, a32, opc);
947
+ TCGv_va addr = gen_aa32_addr(s, a32, opc);
948
949
tcg_gen_qemu_ld_i64(val, addr, index, opc);
950
@@ -956,7 +957,7 @@ void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
957
void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
958
TCGv_i32 a32, int index, MemOp opc)
959
{
959
- TCGv addr = gen_aa32_addr(s, a32, opc);
960
+ TCGv_va addr = gen_aa32_addr(s, a32, opc);
961
962
/* Not needed for user-mode BE32, where we use MO_BE instead. */
963
if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
@@ -2036,7 +2037,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
2037
* architecturally 64-bit access, but instead do a 64-bit access
2038
* using MO_BE if appropriate and then split the two halves.
2039
*/
2039
- TCGv taddr = gen_aa32_addr(s, addr, opc);
2040
+ TCGv_va taddr = gen_aa32_addr(s, addr, opc);
2041
2042
tcg_gen_qemu_ld_i64(t64, taddr, get_mem_index(s), opc);
2043
tcg_gen_mov_i64(cpu_exclusive_val, t64);
@@ -2065,7 +2066,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
2066
{
2067
TCGv_i32 t0, t1, t2;
2068
TCGv_i64 extaddr;
2068
- TCGv taddr;
2069
+ TCGv_va taddr;
2070
TCGLabel *done_label;
2071
TCGLabel *fail_label;
2072
MemOp opc = size | MO_ALIGN | s->be_data;
@@ -3792,7 +3793,7 @@ static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
3793
*/
3794
int mem_idx = get_mem_index(s);
3795
MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;
3795
- TCGv taddr = gen_aa32_addr(s, addr, opc);
3796
+ TCGv_va taddr = gen_aa32_addr(s, addr, opc);
3797
TCGv_i64 t64 = tcg_temp_new_i64();
3798
TCGv_i32 tmp = tcg_temp_new_i32();
3799
TCGv_i32 tmp2 = tcg_temp_new_i32();
@@ -3847,7 +3848,7 @@ static void do_strd_store(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
3848
*/
3849
int mem_idx = get_mem_index(s);
3850
MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;
3850
- TCGv taddr = gen_aa32_addr(s, addr, opc);
3851
+ TCGv_va taddr = gen_aa32_addr(s, addr, opc);
3852
TCGv_i32 t1 = load_reg(s, rt);
3853
TCGv_i32 t2 = load_reg(s, rt2);
3854
TCGv_i64 t64 = tcg_temp_new_i64();
@@ -4068,7 +4069,7 @@ DO_LDST(STRH, store, MO_UW)
4069
static bool op_swp(DisasContext *s, arg_SWP *a, MemOp opc)
4070
{
4071
TCGv_i32 addr, tmp;
4071
- TCGv taddr;
4072
+ TCGv_va taddr;
4073
4074
opc |= s->be_data;
4075
addr = load_reg(s, a->rn);