disas/riscv: Handle aliases of csrrwi during decode
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260812223142.349142-25-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Richard Henderson committed
Aug 12, 2026 at 15:31 UTC
9803e8277307e153dbbb1757c083167f882a9ef8
2 files changed
+8
-22
disas/riscv.c
+8
-20
@@ -1063,8 +1063,6 @@ static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
1063
rvc_end };
1064
static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
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rvc_end };
1066
-static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end };
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-static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end };
1066
1067
/* pseudo-instruction metadata */
1068
@@ -1145,12 +1143,6 @@ static const rv_comp_data rvcp_subw[] = {
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{ rv_op_illegal, NULL }
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};
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-static const rv_comp_data rvcp_csrrwi[] = {
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- { rv_op_fsrmi, rvcc_fsrmi },
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- { rv_op_fsflagsi, rvcc_fsflagsi },
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- { rv_op_illegal, NULL }
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-};
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-
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static const rv_comp_data rvcp_fsgnj_s[] = {
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{ rv_op_fmv_s, rvcc_fmv_s },
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{ rv_op_illegal, NULL }
@@ -1722,7 +1714,7 @@ static const rv_opcode_data rvi_opcode_data[] = {
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{ "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
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{ "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
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{ "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
1725
- { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi },
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+ { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
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{ "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
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{ "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
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{ "flw", rv_codec_i, rv_fmt_frd_offset_rs1 },
@@ -4469,7 +4461,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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}
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}
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break;
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- case 5: op = rv_op_csrrwi; break;
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+ case 5:
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+ switch (operand_csr12(inst)) {
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+ case 1: op = rv_op_fsflagsi; break;
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+ case 2: op = rv_op_fsrmi; break;
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+ default: op = rv_op_csrrwi; break;
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+ }
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+ break;
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case 6: op = rv_op_csrrsi; break;
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case 7: op = rv_op_csrrci; break;
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}
@@ -4991,16 +4989,6 @@ static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
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return false;
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}
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break;
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- case rvc_csr_eq_0x001:
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- if (!(imm == 0x001)) {
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- return false;
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- }
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- break;
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- case rvc_csr_eq_0x002:
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- if (!(imm == 0x002)) {
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- return false;
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- }
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- break;
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default: break;
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}
4994
c++;
disas/riscv.h
-2
@@ -84,8 +84,6 @@ typedef enum {
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rvc_imm_eq_zero,
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rvc_imm_eq_n1,
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rvc_imm_eq_p1,
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- rvc_csr_eq_0x001,
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- rvc_csr_eq_0x002,
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} rvc_constraint;
88
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typedef enum {