hw/riscv: Refactor riscv_iommu_ctx_put() for Bare mode handling
Align SPEC: Bare mode contexts are not cached, so they require direct memory deallocation via g_free instead of hash table cleanup. Signed-off-by: Jay Chang <jay.chang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Message-ID: <20260518072239.16293-3-jay.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Jay Chang committed
May 18, 2026 at 15:22 UTC
9869b871eb52f97171a74613d052c8cce6d9a04d
1 file changed
+10
-1
hw/riscv/riscv-iommu.c
+10
-1
@@ -1390,7 +1390,16 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
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static void riscv_iommu_ctx_put(RISCVIOMMUState *s, void *ref)
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{
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- if (ref) {
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+ unsigned mode = get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE);
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+
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+ if (!ref) {
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+ return;
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+ }
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+
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+ /* ref is pointing to ctx in Bare mode. Bare mode ctx is not cached */
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+ if (mode == RISCV_IOMMU_DDTP_MODE_BARE) {
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+ g_free(ref);
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+ } else {
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g_hash_table_unref((GHashTable *)ref);
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}
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}