hw/misc/zynq_slcr.c: drop duplicate reset value for DDRIOB_DCI_CTRL

When adding a reset value for DDRIOB_DCI_CTRL in c8ba862dbfdc, we haven't noticed that a reset value already exists. DDRIOB is a 32 bit register, so incrementing it by 12 will access the DDRIOB_DCI_CTRL register. According to the manual [1] the correct reset value is 0x00000020. Additionally, c8ba862dbfdc won't work with a reset value of 0x00000021 because it tries to detect a toggle of the reset bit (bit 0). Therefore, we drop the old reset value and keep the new one introduced in c8ba862dbfdc. [1] https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Register-slcr-DDRIOB_DCI_CTRL Fixes: c8ba862dbfdc ("hw/misc/zynq_slcr: Add logic for DCI configuration") Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20260707145407.70287-1-corvin.koehne@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>