target/arm: Re-use common aarch64_aa32_a57_init() helper
Make aarch64_aa32_a57_init() common by exposing its prototype and defining it in cpu-max.c. Call it in arm_max_initfn() restricted to AArch32. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20260526203722.79463-15-philmd@linaro.org>
Philippe Mathieu-Daudé committed
May 13, 2026 at 11:35 UTC
98f7a207aba4062d7000c54364bc156a0ba9f855
4 files changed
+77
-117
target/arm/cpu-max.c
+74
@@ -7,7 +7,81 @@
7
*/
8
9
#include "qemu/osdep.h"
10
+#include "qemu/units.h"
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+#include "system/kvm.h"
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#include "target/arm/internals.h"
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+#include "target/arm/cpregs.h"
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+
15
+void aarch64_aa32_a57_init(Object *obj, bool aa32_only)
16
+{
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+ ARMCPU *cpu = ARM_CPU(obj);
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+ ARMISARegisters *isar = &cpu->isar;
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+ const bool aarch64_enabled = !aa32_only;
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+
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+ cpu->dtb_compatible = "arm,cortex-a57";
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+ set_feature(&cpu->env, ARM_FEATURE_V8);
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+ set_feature(&cpu->env, ARM_FEATURE_NEON);
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+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
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+ if (aarch64_enabled) {
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+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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+ }
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+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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+ set_feature(&cpu->env, ARM_FEATURE_EL2);
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+ set_feature(&cpu->env, ARM_FEATURE_EL3);
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+ set_feature(&cpu->env, ARM_FEATURE_PMU);
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+ if (kvm_enabled()) {
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+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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+ }
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+ cpu->midr = 0x411fd070;
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+ cpu->revidr = 0x00000000;
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+ cpu->reset_fpsid = 0x41034070;
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+ cpu->isar.mvfr0 = 0x10110222;
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+ cpu->isar.mvfr1 = 0x12111111;
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+ cpu->isar.mvfr2 = 0x00000043;
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+ cpu->ctr = 0x8444c004;
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+ cpu->reset_sctlr = 0x00c50838;
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+ SET_IDREG(isar, ID_PFR0, 0x00000131);
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+ SET_IDREG(isar, ID_PFR1, 0x00011011);
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+ SET_IDREG(isar, ID_DFR0, 0x03010066);
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+ SET_IDREG(isar, ID_AFR0, 0x00000000);
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+ SET_IDREG(isar, ID_MMFR0, 0x10101105);
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+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
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+ SET_IDREG(isar, ID_MMFR2, 0x01260000);
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+ SET_IDREG(isar, ID_MMFR3, 0x02102211);
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+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
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+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
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+ SET_IDREG(isar, ID_ISAR2, 0x21232042);
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+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
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+ SET_IDREG(isar, ID_ISAR4, 0x00011142);
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+ SET_IDREG(isar, ID_ISAR5, 0x00011121);
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+ SET_IDREG(isar, ID_ISAR6, 0);
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+ if (aarch64_enabled) {
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+ SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
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+ SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
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+ SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
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+ SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
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+ }
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+ cpu->isar.dbgdidr = 0x3516d000;
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+ cpu->isar.dbgdevid = 0x01110f13;
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+ cpu->isar.dbgdevid1 = 0x2;
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+ cpu->isar.reset_pmcr_el0 = 0x41013000;
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+ SET_IDREG(isar, CLIDR, 0x0a200023);
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+ /* 32KB L1 dcache */
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+ cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
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+ /* 48KB L1 icache */
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+ cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
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+ /* 2048KB L2 cache */
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+ cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
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+ if (aarch64_enabled) {
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+ set_dczid_bs(cpu, 4); /* 64 bytes */
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+ cpu->gic_num_lrs = 4;
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+ cpu->gic_vpribits = 5;
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+ cpu->gic_vprebits = 5;
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+ cpu->gic_pribits = 5;
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+ }
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+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
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+}
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/* Share AArch32 -cpu max features with AArch64. */
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void aa32_max_features(ARMCPU *cpu)
target/arm/cpu64.c
-71
@@ -686,77 +686,6 @@ void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
686
SET_IDREG(&cpu->isar, ID_AA64MMFR0, t);
687
}
688
689
-static void aarch64_aa32_a57_init(Object *obj, bool aa32_only)
690
-{
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- ARMCPU *cpu = ARM_CPU(obj);
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- ARMISARegisters *isar = &cpu->isar;
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- const bool aarch64_enabled = !aa32_only;
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-
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- cpu->dtb_compatible = "arm,cortex-a57";
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- set_feature(&cpu->env, ARM_FEATURE_V8);
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- set_feature(&cpu->env, ARM_FEATURE_NEON);
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- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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- set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
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- if (aarch64_enabled) {
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- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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- }
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- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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- set_feature(&cpu->env, ARM_FEATURE_EL2);
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- set_feature(&cpu->env, ARM_FEATURE_EL3);
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- set_feature(&cpu->env, ARM_FEATURE_PMU);
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- if (kvm_enabled()) {
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- cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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- }
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- cpu->midr = 0x411fd070;
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- cpu->revidr = 0x00000000;
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- cpu->reset_fpsid = 0x41034070;
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- cpu->isar.mvfr0 = 0x10110222;
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- cpu->isar.mvfr1 = 0x12111111;
715
- cpu->isar.mvfr2 = 0x00000043;
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- cpu->ctr = 0x8444c004;
717
- cpu->reset_sctlr = 0x00c50838;
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- SET_IDREG(isar, ID_PFR0, 0x00000131);
719
- SET_IDREG(isar, ID_PFR1, 0x00011011);
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- SET_IDREG(isar, ID_DFR0, 0x03010066);
721
- SET_IDREG(isar, ID_AFR0, 0x00000000);
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- SET_IDREG(isar, ID_MMFR0, 0x10101105);
723
- SET_IDREG(isar, ID_MMFR1, 0x40000000);
724
- SET_IDREG(isar, ID_MMFR2, 0x01260000);
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- SET_IDREG(isar, ID_MMFR3, 0x02102211);
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- SET_IDREG(isar, ID_ISAR0, 0x02101110);
727
- SET_IDREG(isar, ID_ISAR1, 0x13112111);
728
- SET_IDREG(isar, ID_ISAR2, 0x21232042);
729
- SET_IDREG(isar, ID_ISAR3, 0x01112131);
730
- SET_IDREG(isar, ID_ISAR4, 0x00011142);
731
- SET_IDREG(isar, ID_ISAR5, 0x00011121);
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- SET_IDREG(isar, ID_ISAR6, 0);
733
- if (aarch64_enabled) {
734
- SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
735
- SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
736
- SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
737
- SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
738
- }
739
- cpu->isar.dbgdidr = 0x3516d000;
740
- cpu->isar.dbgdevid = 0x01110f13;
741
- cpu->isar.dbgdevid1 = 0x2;
742
- cpu->isar.reset_pmcr_el0 = 0x41013000;
743
- SET_IDREG(isar, CLIDR, 0x0a200023);
744
- /* 32KB L1 dcache */
745
- cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
746
- /* 48KB L1 icache */
747
- cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
748
- /* 2048KB L2 cache */
749
- cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
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- if (aarch64_enabled) {
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- set_dczid_bs(cpu, 4); /* 64 bytes */
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- cpu->gic_num_lrs = 4;
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- cpu->gic_vpribits = 5;
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- cpu->gic_vprebits = 5;
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- cpu->gic_pribits = 5;
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- }
757
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
758
-}
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-
689
static void aarch64_a57_initfn(Object *obj)
690
{
691
aarch64_aa32_a57_init(obj, false);
target/arm/internals.h
+1
@@ -1773,6 +1773,7 @@ void aarch64_max_tcg_initfn(Object *obj);
1773
void aarch64_add_pauth_properties(Object *obj);
1774
void aarch64_add_sve_properties(Object *obj);
1775
void aarch64_add_sme_properties(Object *obj);
1776
+void aarch64_aa32_a57_init(Object *obj, bool aa32_only);
1777
1778
/* Return true if the gdbstub is presenting an AArch64 CPU */
1779
static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu)
target/arm/tcg/cpu32.c
+2
-46
@@ -720,53 +720,9 @@ static void sa1110_initfn(Object *obj)
720
static void arm_max_initfn(Object *obj)
721
{
722
ARMCPU *cpu = ARM_CPU(obj);
723
- ARMISARegisters *isar = &cpu->isar;
723
725
- /* aarch64_a57_initfn, advertising none of the aarch64 features */
726
- cpu->dtb_compatible = "arm,cortex-a57";
727
- set_feature(&cpu->env, ARM_FEATURE_V8);
728
- set_feature(&cpu->env, ARM_FEATURE_NEON);
729
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
730
- set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
731
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
732
- set_feature(&cpu->env, ARM_FEATURE_EL2);
733
- set_feature(&cpu->env, ARM_FEATURE_EL3);
734
- set_feature(&cpu->env, ARM_FEATURE_PMU);
735
- cpu->midr = 0x411fd070;
736
- cpu->revidr = 0x00000000;
737
- cpu->reset_fpsid = 0x41034070;
738
- cpu->isar.mvfr0 = 0x10110222;
739
- cpu->isar.mvfr1 = 0x12111111;
740
- cpu->isar.mvfr2 = 0x00000043;
741
- cpu->ctr = 0x8444c004;
742
- cpu->reset_sctlr = 0x00c50838;
743
- SET_IDREG(isar, ID_PFR0, 0x00000131);
744
- SET_IDREG(isar, ID_PFR1, 0x00011011);
745
- SET_IDREG(isar, ID_DFR0, 0x03010066);
746
- SET_IDREG(isar, ID_AFR0, 0x00000000);
747
- SET_IDREG(isar, ID_MMFR0, 0x10101105);
748
- SET_IDREG(isar, ID_MMFR1, 0x40000000);
749
- SET_IDREG(isar, ID_MMFR2, 0x01260000);
750
- SET_IDREG(isar, ID_MMFR3, 0x02102211);
751
- SET_IDREG(isar, ID_ISAR0, 0x02101110);
752
- SET_IDREG(isar, ID_ISAR1, 0x13112111);
753
- SET_IDREG(isar, ID_ISAR2, 0x21232042);
754
- SET_IDREG(isar, ID_ISAR3, 0x01112131);
755
- SET_IDREG(isar, ID_ISAR4, 0x00011142);
756
- SET_IDREG(isar, ID_ISAR5, 0x00011121);
757
- SET_IDREG(isar, ID_ISAR6, 0);
758
- cpu->isar.dbgdidr = 0x3516d000;
759
- cpu->isar.dbgdevid = 0x01110f13;
760
- cpu->isar.dbgdevid1 = 0x2;
761
- cpu->isar.reset_pmcr_el0 = 0x41013000;
762
- SET_IDREG(isar, CLIDR, 0x0a200023);
763
- /* 32KB L1 dcache */
764
- cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
765
- /* 48KB L1 icache */
766
- cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
767
- /* 2048KB L2 cache */
768
- cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
769
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
724
+ /* Cortex-A57 advertising none of the aarch64 features */
725
+ aarch64_aa32_a57_init(obj, true);
726
727
aa32_max_features(cpu);
728