target/arm: Implement FEAT_FAMINMAX for SVE
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260522220306.235200-5-richard.henderson@linaro.org [PMM: add comments for TRANS_ macros] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
May 22, 2026 at 15:02 UTC
9972384eb3a7bd2dfed7e16d3d0caaecf2d80631
6 files changed
+67
target/arm/cpu-features.h
+11
@@ -1568,6 +1568,11 @@ static inline bool isar_feature_aa64_sme_or_sve2(const ARMISARegisters *id)
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return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2(id);
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}
1570
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+static inline bool isar_feature_aa64_sme2_or_sve2(const ARMISARegisters *id)
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+{
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+ return isar_feature_aa64_sme2(id) || isar_feature_aa64_sve2(id);
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+}
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+
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static inline bool isar_feature_aa64_sme_or_sve2p1(const ARMISARegisters *id)
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{
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return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2p1(id);
@@ -1608,6 +1613,12 @@ static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
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return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_bf16(id);
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}
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+static inline bool
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+isar_feature_aa64_sme2_or_sve2_faminmax(const ARMISARegisters *id)
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+{
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+ return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_faminmax(id);
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+}
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+
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/*
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* Feature tests for "does this exist in either 32-bit or 64-bit?"
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*/
target/arm/tcg/helper-sve-defs.h
+14
@@ -3180,3 +3180,17 @@ DEF_HELPER_FLAGS_5(sve2p1_st1ss_le_c, TCG_CALL_NO_WG, void, env, ptr, tl, i32, i
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DEF_HELPER_FLAGS_5(sve2p1_st1ss_be_c, TCG_CALL_NO_WG, void, env, ptr, tl, i32, i64)
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DEF_HELPER_FLAGS_5(sve2p1_st1dd_le_c, TCG_CALL_NO_WG, void, env, ptr, tl, i32, i64)
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DEF_HELPER_FLAGS_5(sve2p1_st1dd_be_c, TCG_CALL_NO_WG, void, env, ptr, tl, i32, i64)
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+
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+DEF_HELPER_FLAGS_6(sve2_famax_h, TCG_CALL_NO_RWG,
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+ void, ptr, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_6(sve2_famax_s, TCG_CALL_NO_RWG,
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+ void, ptr, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_6(sve2_famax_d, TCG_CALL_NO_RWG,
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+ void, ptr, ptr, ptr, ptr, fpst, i32)
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+
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+DEF_HELPER_FLAGS_6(sve2_famin_h, TCG_CALL_NO_RWG,
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+ void, ptr, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_6(sve2_famin_s, TCG_CALL_NO_RWG,
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+ void, ptr, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_6(sve2_famin_d, TCG_CALL_NO_RWG,
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+ void, ptr, ptr, ptr, ptr, fpst, i32)
target/arm/tcg/sve.decode
+2
@@ -1130,6 +1130,8 @@ FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm
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FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm
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FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR
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FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm
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+FAMAX 01100101 .. 00 1110 100 ... ..... ..... @rdn_pg_rm
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+FAMIN 01100101 .. 00 1111 100 ... ..... ..... @rdn_pg_rm
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# SVE floating-point arithmetic with immediate (predicated)
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FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1
target/arm/tcg/sve_helper.c
+8
@@ -4750,6 +4750,14 @@ DO_ZPZZ_FP(sve_fmulx_h, uint16_t, H1_2, helper_advsimd_mulxh)
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DO_ZPZZ_FP(sve_fmulx_s, uint32_t, H1_4, helper_vfp_mulxs)
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DO_ZPZZ_FP(sve_fmulx_d, uint64_t, H1_8, helper_vfp_mulxd)
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+DO_ZPZZ_FP(sve2_famax_h, uint16_t, H1_2, float16_famax)
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+DO_ZPZZ_FP(sve2_famax_s, uint32_t, H1_4, float32_famax)
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+DO_ZPZZ_FP(sve2_famax_d, uint64_t, H1_8, float64_famax)
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+
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+DO_ZPZZ_FP(sve2_famin_h, uint16_t, H1_2, float16_famin)
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+DO_ZPZZ_FP(sve2_famin_s, uint32_t, H1_4, float32_famin)
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+DO_ZPZZ_FP(sve2_famin_d, uint64_t, H1_8, float64_famin)
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+
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#undef DO_ZPZZ_FP
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/* Three-operand expander, with one scalar operand, controlled by
target/arm/tcg/translate-sve.c
+20
@@ -4254,6 +4254,26 @@ DO_ZPZZ_FP(FSCALE, aa64_sme_or_sve, sve_fscalbn)
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DO_ZPZZ_FP(FDIV, aa64_sme_or_sve, sve_fdiv)
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DO_ZPZZ_FP(FMULX, aa64_sme_or_sve, sve_fmulx)
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+static gen_helper_gvec_4_ptr * const sve2_famax_zpzz_fns[4] = {
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+ NULL,
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+ gen_helper_sve2_famax_h,
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+ gen_helper_sve2_famax_s,
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+ gen_helper_sve2_famax_d
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+};
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+TRANS_FEAT_STREAMING_SME2(FAMAX, aa64_sme2_or_sve2_faminmax,
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+ gen_gvec_fpst_arg_zpzz,
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+ sve2_famax_zpzz_fns[a->esz], a)
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+
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+static gen_helper_gvec_4_ptr * const sve2_famin_zpzz_fns[4] = {
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+ NULL,
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+ gen_helper_sve2_famin_h,
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+ gen_helper_sve2_famin_s,
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+ gen_helper_sve2_famin_d
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+};
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+TRANS_FEAT_STREAMING_SME2(FAMIN, aa64_sme2_or_sve2_faminmax,
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+ gen_gvec_fpst_arg_zpzz,
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+ sve2_famin_zpzz_fns[a->esz], a)
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+
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typedef void gen_helper_sve_fp2scalar(TCGv_ptr, TCGv_ptr, TCGv_ptr,
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TCGv_i64, TCGv_ptr, TCGv_i32);
4279
target/arm/tcg/translate.h
+12
@@ -865,6 +865,7 @@ static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)
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static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
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{ return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
867
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+/* For SVE insns which are not valid in Streaming SVE mode */
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#define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \
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static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
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{ \
@@ -872,4 +873,15 @@ static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)
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return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \
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}
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+/*
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+ * For SVE insns which are only valid in Streaming SVE mode when
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+ * SME2 is implemented
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+ */
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+#define TRANS_FEAT_STREAMING_SME2(NAME, FEAT, FUNC, ...) \
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+ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
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+ { \
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+ s->is_nonstreaming = !dc_isar_feature(aa64_sme2, s); \
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+ return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \
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+ }
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+
887
#endif /* TARGET_ARM_TRANSLATE_H */