target/arm: Implement CB (immediate)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260518174750.660258-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: var decl at top of function; add comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
May 18, 2026 at 10:47 UTC
9ad7cc13862645992a10fdc65583284d7bd2f773
2 files changed
+45
target/arm/tcg/a64.decode
+2
@@ -217,6 +217,8 @@ CB_cond 1 1110100 ... ..... 00 ......... ..... @cb esz=3
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CB_cond 0 1110100 ... ..... 10 ......... ..... @cb esz=0 # CBB
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CB_cond 0 1110100 ... ..... 11 ......... ..... @cb esz=1 # CBH
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+CB_cond_imm sf:1 1110101 cc:3 imm6:6 0 ......... rt:5 %imm9
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+
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BR 1101011 0000 11111 000000 rn:5 00000 &r
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BLR 1101011 0001 11111 000000 rn:5 00000 &r
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RET 1101011 0010 11111 000000 rn:5 00000 &r
target/arm/tcg/translate-a64.c
+43
@@ -1817,6 +1817,49 @@ static bool trans_CB_cond(DisasContext *s, arg_CB_cond *a)
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return true;
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}
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+static bool trans_CB_cond_imm(DisasContext *s, arg_CB_cond_imm *a)
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+{
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+ /* Note that CB imm and CB encode the condition differently */
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+ static const TCGCond cb_cond[8] = {
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+ [0] = TCG_COND_GT,
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+ [1] = TCG_COND_LT,
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+ [2] = TCG_COND_GTU,
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+ [3] = TCG_COND_LTU,
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+ [4] = TCG_COND_NEVER, /* reserved */
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+ [5] = TCG_COND_NEVER, /* reserved */
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+ [6] = TCG_COND_EQ,
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+ [7] = TCG_COND_NE,
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+ };
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+ TCGCond cond = cb_cond[a->cc];
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+ TCGv_i64 t;
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+ DisasLabel match;
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+
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+ if (!dc_isar_feature(aa64_cmpbr, s) || cond == TCG_COND_NEVER) {
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+ return false;
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+ }
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+
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+ t = cpu_reg(s, a->rt);
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+ if (!a->sf) {
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+ TCGv_i64 tt = tcg_temp_new_i64();
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+
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+ if (is_signed_cond(cond)) {
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+ tcg_gen_ext32s_i64(tt, t);
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+ } else {
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+ tcg_gen_ext32u_i64(tt, t);
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+ }
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+ t = tt;
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+ }
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+
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+ reset_btype(s);
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+ match = gen_disas_label(s);
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+
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+ tcg_gen_brcondi_i64(cond, t, a->imm6, match.label);
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+ gen_goto_tb(s, 0, 4);
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+ set_disas_label(s, match);
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+ gen_goto_tb(s, 1, a->imm9);
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+ return true;
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+}
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+
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static void set_btype_for_br(DisasContext *s, int rn)
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{
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if (dc_isar_feature(aa64_bti, s)) {